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From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
To: "Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	johan+linaro@kernel.org, bmasney@redhat.com, djakov@kernel.org
Cc: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<vireshk@kernel.org>, <quic_vbadigan@quicinc.com>,
	<quic_skananth@quicinc.com>, <quic_nitegupt@quicinc.com>,
	<quic_parass@quicinc.com>, <quic_krichai@quicinc.com>,
	<krzysztof.kozlowski@linaro.org>
Subject: [PATCH v10 4/6] arm64: dts: qcom: sm8450: Add OPP table support to PCIe
Date: Tue, 9 Apr 2024 15:43:22 +0530	[thread overview]
Message-ID: <20240409-opp_support-v10-4-1956e6be343f@quicinc.com> (raw)
In-Reply-To: <20240409-opp_support-v10-0-1956e6be343f@quicinc.com>

PCIe needs to choose the appropriate performance state of RPMh power
domain and interconnect bandwidth based up on the PCIe data rate.

Add the OPP table support to specify RPMh performance states and
interconnect peak bandwidth.

Different link configurations may share the same aggregate bandwidth,
e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1 link have the same bandwidth
and share the same OPP entry.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 77 ++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 615296e13c43..9dfe16012726 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1855,7 +1855,35 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie0_default_state>;
 
+			operating-points-v2 = <&pcie0_opp_table>;
+
 			status = "disabled";
+
+			pcie0_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/* GEN 1 x1 */
+				opp-2500000 {
+					opp-hz = /bits/ 64 <2500000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <250000 1>;
+				};
+
+				/* GEN 2 x1 */
+				opp-5000000 {
+					opp-hz = /bits/ 64 <5000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <500000 1>;
+				};
+
+				/* GEN 3 x1 */
+				opp-8000000 {
+					opp-hz = /bits/ 64 <8000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+					opp-peak-kBps = <984500 1>;
+				};
+			};
+
 		};
 
 		pcie0_phy: phy@1c06000 {
@@ -1982,7 +2010,56 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_default_state>;
 
+			operating-points-v2 = <&pcie1_opp_table>;
+
 			status = "disabled";
+
+			pcie1_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/* GEN 1 x1 */
+				opp-2500000 {
+					opp-hz = /bits/ 64 <2500000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <250000 1>;
+				};
+
+				/* GEN 1 x2 GEN 2 x1 */
+				opp-5000000 {
+					opp-hz = /bits/ 64 <5000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <500000 1>;
+				};
+
+				/* GEN 2 x2 */
+				opp-10000000 {
+					opp-hz = /bits/ 64 <10000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <1000000 1>;
+				};
+
+				/* GEN 3 x1 */
+				opp-8000000 {
+					opp-hz = /bits/ 64 <8000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+					opp-peak-kBps = <984500 1>;
+				};
+
+				/* GEN 3 x2 GEN 4 x1 */
+				opp-16000000 {
+					opp-hz = /bits/ 64 <16000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+					opp-peak-kBps = <1969000 1>;
+				};
+
+				/* GEN 4 x2 */
+				opp-32000000 {
+					opp-hz = /bits/ 64 <32000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+					opp-peak-kBps = <3938000 1>;
+				};
+			};
+
 		};
 
 		pcie1_phy: phy@1c0e000 {

-- 
2.42.0


  parent reply	other threads:[~2024-04-09 10:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-09 10:13 [PATCH v10 0/6] PCI: qcom: Add support for OPP Krishna chaitanya chundru
2024-04-09 10:13 ` [PATCH v10 1/6] arm64: dts: qcom: sm8450: Add interconnect path to PCIe node Krishna chaitanya chundru
2024-04-09 10:13 ` [PATCH v10 2/6] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path Krishna chaitanya chundru
2024-04-22 14:31   ` Manivannan Sadhasivam
2024-04-09 10:13 ` [PATCH v10 3/6] dt-bindings: pci: qcom: Add OPP table Krishna chaitanya chundru
2024-04-09 10:13 ` Krishna chaitanya chundru [this message]
2024-04-22 14:44   ` [PATCH v10 4/6] arm64: dts: qcom: sm8450: Add OPP table support to PCIe Manivannan Sadhasivam
2024-04-22 16:55     ` Krishna Chaitanya Chundru
2024-04-22 17:08       ` Manivannan Sadhasivam
2024-04-09 10:13 ` [PATCH v10 5/6] PCI: Bring the PCIe speed to MBps logic to new pcie_link_speed_to_mbps() Krishna chaitanya chundru
2024-04-09 15:07   ` Bjorn Helgaas
2024-04-09 10:13 ` [PATCH v10 6/6] PCI: qcom: Add OPP support to scale performance state of power domain Krishna chaitanya chundru

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