From: Andy Chiu <andy.chiu@sifive.com> To: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Conor Dooley" <conor.dooley@microchip.com>, "Heiko Stuebner" <heiko@sntech.de>, "Andy Chiu" <andy.chiu@sifive.com>, "Guo Ren" <guoren@kernel.org>, "Conor Dooley" <conor@kernel.org>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Jonathan Corbet" <corbet@lwn.net>, "Evan Green" <evan@rivosinc.com>, "Clément Léger" <cleger@rivosinc.com>, "Shuah Khan" <shuah@kernel.org> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>, Vincent Chen <vincent.chen@sifive.com>, Greentime Hu <greentime.hu@sifive.com>, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH v4 2/9] riscv: smp: fail booting up smp if inconsistent vlen is detected Date: Fri, 12 Apr 2024 14:48:58 +0800 [thread overview] Message-ID: <20240412-zve-detection-v4-2-e0c45bb6b253@sifive.com> (raw) In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context") Reported-by: Conor Dooley <conor.dooley@microchip.com> Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/ Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- Changelog v4: - update comment also in the assembly code (Yunhui) Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 19 ++++++++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a00f7523cb91 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,20 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ +.align 2 +.Lsecondary_park: + /* + * Park this hart if we: + * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT + * - receive an early trap, before setup_trap_vector finished + * - fail in smp_callin(), as a successful one wouldn't return + */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +192,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d41090fc3203..673437ccc13d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -214,6 +214,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm = mm; @@ -226,11 +235,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &= ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); /* -- 2.44.0.rc2
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Conor Dooley" <conor.dooley@microchip.com>, "Heiko Stuebner" <heiko@sntech.de>, "Andy Chiu" <andy.chiu@sifive.com>, "Guo Ren" <guoren@kernel.org>, "Conor Dooley" <conor@kernel.org>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Jonathan Corbet" <corbet@lwn.net>, "Evan Green" <evan@rivosinc.com>, "Clément Léger" <cleger@rivosinc.com>, "Shuah Khan" <shuah@kernel.org> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>, Vincent Chen <vincent.chen@sifive.com>, Greentime Hu <greentime.hu@sifive.com>, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH v4 2/9] riscv: smp: fail booting up smp if inconsistent vlen is detected Date: Fri, 12 Apr 2024 14:48:58 +0800 [thread overview] Message-ID: <20240412-zve-detection-v4-2-e0c45bb6b253@sifive.com> (raw) In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context") Reported-by: Conor Dooley <conor.dooley@microchip.com> Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/ Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- Changelog v4: - update comment also in the assembly code (Yunhui) Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 19 ++++++++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a00f7523cb91 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,20 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ +.align 2 +.Lsecondary_park: + /* + * Park this hart if we: + * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT + * - receive an early trap, before setup_trap_vector finished + * - fail in smp_callin(), as a successful one wouldn't return + */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +192,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d41090fc3203..673437ccc13d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -214,6 +214,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm = mm; @@ -226,11 +235,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &= ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); /* -- 2.44.0.rc2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-12 6:49 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-12 6:48 [PATCH v4 0/9] Support Zve32[xf] and Zve64[xfd] Vector subextensions Andy Chiu 2024-04-12 6:48 ` Andy Chiu 2024-04-12 6:48 ` [PATCH v4 1/9] riscv: vector: add a comment when calling riscv_setup_vsize() Andy Chiu 2024-04-12 6:48 ` Andy Chiu 2024-04-18 9:54 ` Conor Dooley 2024-04-18 9:54 ` Conor Dooley 2024-04-12 6:48 ` Andy Chiu [this message] 2024-04-12 6:48 ` [PATCH v4 2/9] riscv: smp: fail booting up smp if inconsistent vlen is detected Andy Chiu 2024-04-18 10:17 ` Conor Dooley 2024-04-18 10:17 ` Conor Dooley 2024-04-19 6:09 ` [External] " yunhui cui 2024-04-19 6:09 ` yunhui cui 2024-04-24 20:01 ` Alexandre Ghiti 2024-04-24 20:01 ` Alexandre Ghiti 2024-05-08 8:21 ` Andy Chiu 2024-05-08 8:21 ` Andy Chiu 2024-05-08 10:43 ` Alexandre Ghiti 2024-05-08 10:43 ` Alexandre Ghiti 2024-04-12 6:48 ` [PATCH v4 3/9] riscv: cpufeature: call match_isa_ext() for single-letter extensions Andy Chiu 2024-04-12 6:48 ` Andy Chiu 2024-04-18 10:29 ` Conor Dooley 2024-04-18 10:29 ` Conor Dooley 2024-04-12 6:49 ` [PATCH v4 4/9] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Andy Chiu 2024-04-12 6:49 ` Andy Chiu 2024-04-18 10:19 ` Conor Dooley 2024-04-18 10:19 ` Conor Dooley 2024-04-12 6:49 ` [PATCH v4 5/9] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description Andy Chiu 2024-04-12 6:49 ` Andy Chiu 2024-04-18 10:21 ` Conor Dooley 2024-04-18 10:21 ` Conor Dooley 2024-04-12 6:49 ` [PATCH v4 6/9] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Andy Chiu 2024-04-12 6:49 ` Andy Chiu 2024-04-12 6:49 ` [PATCH v4 7/9] riscv: vector: adjust minimum Vector requirement to ZVE32X Andy Chiu 2024-04-12 6:49 ` Andy Chiu 2024-04-18 11:02 ` Conor Dooley 2024-04-18 11:02 ` Conor Dooley 2024-04-18 15:52 ` Eric Biggers 2024-04-18 15:52 ` Eric Biggers 2024-04-18 16:53 ` Conor Dooley 2024-04-18 16:53 ` Conor Dooley 2024-04-18 17:32 ` Eric Biggers 2024-04-18 17:32 ` Eric Biggers 2024-04-18 17:39 ` Eric Biggers 2024-04-18 17:39 ` Eric Biggers 2024-04-18 18:26 ` Conor Dooley 2024-04-18 18:26 ` Conor Dooley 2024-04-18 18:28 ` Conor Dooley 2024-04-18 18:28 ` Conor Dooley 2024-04-18 18:41 ` Eric Biggers 2024-04-18 18:41 ` Eric Biggers 2024-04-18 20:00 ` Conor Dooley 2024-04-18 20:00 ` Conor Dooley 2024-05-09 6:56 ` Andy Chiu 2024-05-09 6:56 ` Andy Chiu 2024-05-09 7:48 ` Conor Dooley 2024-05-09 7:48 ` Conor Dooley 2024-05-09 8:25 ` Conor Dooley 2024-05-09 8:25 ` Conor Dooley 2024-05-09 22:22 ` Conor Dooley 2024-05-09 22:22 ` Conor Dooley 2024-04-12 6:49 ` [PATCH v4 8/9] hwprobe: fix integer promotion in RISCV_HWPROBE_EXT macro Andy Chiu 2024-04-12 6:49 ` Andy Chiu 2024-04-12 6:49 ` [PATCH v4 9/9] selftest: run vector prctl test for ZVE32X Andy Chiu 2024-04-12 6:49 ` Andy Chiu 2024-04-25 23:00 ` [PATCH v4 0/9] Support Zve32[xf] and Zve64[xfd] Vector subextensions patchwork-bot+linux-riscv 2024-04-25 23:00 ` patchwork-bot+linux-riscv
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20240412-zve-detection-v4-2-e0c45bb6b253@sifive.com \ --to=andy.chiu@sifive.com \ --cc=aou@eecs.berkeley.edu \ --cc=cleger@rivosinc.com \ --cc=conor.dooley@microchip.com \ --cc=conor@kernel.org \ --cc=corbet@lwn.net \ --cc=devicetree@vger.kernel.org \ --cc=evan@rivosinc.com \ --cc=greentime.hu@sifive.com \ --cc=guoren@kernel.org \ --cc=heiko@sntech.de \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-doc@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-kselftest@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=palmer@rivosinc.com \ --cc=paul.walmsley@sifive.com \ --cc=robh@kernel.org \ --cc=shuah@kernel.org \ --cc=vincent.chen@sifive.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.