From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 8/8] drm/i915: Enable per-lane DP drive settings for bxt/glk
Date: Fri, 12 Apr 2024 20:58:18 +0300 [thread overview]
Message-ID: <20240412175818.29217-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20240412175818.29217-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now the bxt/glk PHY code is ready for per-lane drive settings
so enable it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index fb84ca98bb7a..947575140059 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -334,7 +334,7 @@ static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
- DISPLAY_VER(i915) >= 11;
+ DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915);
}
/* 128b/132b */
--
2.43.2
next prev parent reply other threads:[~2024-04-12 17:58 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 17:58 [PATCH 0/8] drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup Ville Syrjala
2024-04-12 17:58 ` [PATCH 1/8] drm/i915/dpio: Clean up bxt/glk PHY registers Ville Syrjala
2024-04-12 17:58 ` [PATCH 2/8] drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk Ville Syrjala
2024-04-15 12:35 ` Jani Nikula
2024-04-15 23:12 ` kernel test robot
2024-04-16 0:28 ` kernel test robot
2024-04-17 15:12 ` [PATCH v2 " Ville Syrjala
2024-04-21 7:06 ` [PATCH " kernel test robot
2024-04-12 17:58 ` [PATCH 3/8] drm/i915/dpio: Extract bxt_dpio_phy_regs.h Ville Syrjala
2024-04-16 1:41 ` kernel test robot
2024-04-17 15:12 ` [PATCH v2 " Ville Syrjala
2024-04-21 10:31 ` [PATCH " kernel test robot
2024-04-12 17:58 ` [PATCH 4/8] drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp() Ville Syrjala
2024-04-15 12:36 ` Jani Nikula
2024-04-12 17:58 ` [PATCH 5/8] drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setup Ville Syrjala
2024-04-12 17:58 ` [PATCH 6/8] drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff Ville Syrjala
2024-04-15 12:39 ` Jani Nikula
2024-04-17 13:04 ` Ville Syrjälä
2024-04-12 17:58 ` [PATCH 7/8] drm/i915/dpio: Program bxt/glk PHY TX registers per-lane Ville Syrjala
2024-04-12 17:58 ` Ville Syrjala [this message]
2024-04-15 12:34 ` [PATCH 0/8] drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup Jani Nikula
2024-04-15 14:29 ` ✗ Fi.CI.BUILD: failure for " Patchwork
2024-04-17 18:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3) Patchwork
2024-04-17 18:07 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-17 18:22 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-18 16:40 ` Jani Nikula
2024-04-19 5:37 ` Musial, Ewelina
2024-04-19 8:31 ` Jani Nikula
2024-04-19 16:56 ` Ville Syrjälä
2024-04-18 23:34 ` ✓ Fi.CI.IGT: " Patchwork
2024-04-19 17:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev4) Patchwork
2024-04-19 17:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-19 18:00 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-20 1:40 ` ✗ Fi.CI.IGT: failure " Patchwork
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