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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 17/18] drm/i915: Unionize dpll_hw_state
Date: Fri, 12 Apr 2024 21:27:02 +0300	[thread overview]
Message-ID: <20240412182703.19916-18-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20240412182703.19916-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dpll_hw_state contains space for all possible PLL
register values across all platforms. That is rather wasteful
as each machine only needs to store the registers values
that are appropriate for the platform.

Turn intel_dpll_hw_state into a union so that we don't
waste memory for the register values of other platforms.

And let's use an anonymous union so that we don't have
to do tons of s/struct/union/ all over the place.

pahole:
 struct intel_dpll_hw_state {
-       struct i9xx_dpll_hw_state  i9xx;                 /*     0    16 */
-       struct hsw_dpll_hw_state   hsw;                  /*    16     8 */
-       struct skl_dpll_hw_state   skl;                  /*    24    12 */
-       struct bxt_dpll_hw_state   bxt;                  /*    36    44 */
-       /* --- cacheline 1 boundary (64 bytes) was 16 bytes ago --- */
-       struct icl_dpll_hw_state   icl;                  /*    80    60 */
+       union {
+               struct i9xx_dpll_hw_state i9xx;          /*     0    16 */
+               struct hsw_dpll_hw_state hsw;            /*     0     8 */
+               struct skl_dpll_hw_state skl;            /*     0    12 */
+               struct bxt_dpll_hw_state bxt;            /*     0    44 */
+               struct icl_dpll_hw_state icl;            /*     0    60 */
+       };                                               /*     0    60 */

-       /* size: 140, cachelines: 3, members: 5 */
-       /* last cacheline: 12 bytes */
+       /* size: 60, cachelines: 1, members: 1 */
+       /* last cacheline: 60 bytes */

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 95438f12c4f0..d0ec6196d398 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -230,11 +230,13 @@ struct icl_dpll_hw_state {
 };
 
 struct intel_dpll_hw_state {
-	struct i9xx_dpll_hw_state i9xx;
-	struct hsw_dpll_hw_state hsw;
-	struct skl_dpll_hw_state skl;
-	struct bxt_dpll_hw_state bxt;
-	struct icl_dpll_hw_state icl;
+	union {
+		struct i9xx_dpll_hw_state i9xx;
+		struct hsw_dpll_hw_state hsw;
+		struct skl_dpll_hw_state skl;
+		struct bxt_dpll_hw_state bxt;
+		struct icl_dpll_hw_state icl;
+	};
 };
 
 /**
-- 
2.43.2


  parent reply	other threads:[~2024-04-12 18:28 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump Ville Syrjala
2024-04-12 18:26 ` [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments Ville Syrjala
2024-04-12 18:26 ` [PATCH 04/18] drm/i915: Introduce some local PLL state variables Ville Syrjala
2024-04-12 18:26 ` [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor() Ville Syrjala
2024-04-12 18:26 ` [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp() Ville Syrjala
2024-04-12 18:26 ` [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable() Ville Syrjala
2024-04-12 18:26 ` [PATCH 09/18] drm/i915: Extract i965_dpll_md() Ville Syrjala
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
2024-04-15 14:06   ` Jani Nikula
2024-04-12 18:26 ` [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers() Ville Syrjala
2024-04-12 18:26 ` [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk() Ville Syrjala
2024-04-12 18:26 ` [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() Ville Syrjala
2024-04-12 18:26 ` [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code Ville Syrjala
2024-04-12 18:27 ` [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables Ville Syrjala
2024-04-12 18:27 ` [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` Ville Syrjala [this message]
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
2024-04-15 14:26   ` Jani Nikula
2024-04-15 14:26 ` [PATCH 00/18] drm/i915: PLL refactoring Jani Nikula
2024-04-15 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-04-15 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-15 15:01 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 19:06 ` ✓ Fi.CI.IGT: " Patchwork

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