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From: Damien Le Moal <dlemoal@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Heiko Stuebner <heiko@sntech.de>,
	linux-pci@vger.kernel.org
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/2] PCI: rockchip-host: Wait 100ms after reset before starting configuration
Date: Sat, 13 Apr 2024 09:41:20 +0900	[thread overview]
Message-ID: <20240413004120.1099089-3-dlemoal@kernel.org> (raw)
In-Reply-To: <20240413004120.1099089-1-dlemoal@kernel.org>

The PCI Express Base Specification r6.0, section 6.6.1, states that the
host should wait for at least 100 msec from the end of a conventional
reset (PERST# is de-asserted) before sending a configuration request to
ensure that the device is able to respond with a "Request Retry Status"
completion.

Add the PCIE_T_RRS_READY_MS macro to define this wait time and modify
rockchip_pcie_host_init_port() to add this 100ms sleep after deasserting
PERST# using the ep_gpio GPIO.

Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
---
 drivers/pci/controller/pcie-rockchip-host.c | 2 ++
 drivers/pci/pci.h                           | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index fc868251e570..cbec71114825 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -325,6 +325,8 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 	msleep(PCIE_T_PVPERL_MS);
 	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
+	msleep(PCIE_T_RRS_READY_MS);
+
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
 				 status, PCIE_LINK_UP(status), 20,
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 17fed1846847..c93ffc5e6e1f 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -16,6 +16,13 @@
 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
 #define PCIE_T_PVPERL_MS		100
 
+/*
+ * End of conventional reset (PERST# de-asserted) to first configuration
+ * request (device able to respond with a "Request Retry Status" completion),
+ * from PCI Express Base Specification r6.0, section 6.6.1.
+ */
+#define PCIE_T_RRS_READY_MS	100
+
 /*
  * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
  * Recommends 1ms to 10ms timeout to check L2 ready.
-- 
2.44.0


WARNING: multiple messages have this Message-ID (diff)
From: Damien Le Moal <dlemoal@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Heiko Stuebner <heiko@sntech.de>,
	linux-pci@vger.kernel.org
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/2] PCI: rockchip-host: Wait 100ms after reset before starting configuration
Date: Sat, 13 Apr 2024 09:41:20 +0900	[thread overview]
Message-ID: <20240413004120.1099089-3-dlemoal@kernel.org> (raw)
In-Reply-To: <20240413004120.1099089-1-dlemoal@kernel.org>

The PCI Express Base Specification r6.0, section 6.6.1, states that the
host should wait for at least 100 msec from the end of a conventional
reset (PERST# is de-asserted) before sending a configuration request to
ensure that the device is able to respond with a "Request Retry Status"
completion.

Add the PCIE_T_RRS_READY_MS macro to define this wait time and modify
rockchip_pcie_host_init_port() to add this 100ms sleep after deasserting
PERST# using the ep_gpio GPIO.

Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
---
 drivers/pci/controller/pcie-rockchip-host.c | 2 ++
 drivers/pci/pci.h                           | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index fc868251e570..cbec71114825 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -325,6 +325,8 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 	msleep(PCIE_T_PVPERL_MS);
 	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
+	msleep(PCIE_T_RRS_READY_MS);
+
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
 				 status, PCIE_LINK_UP(status), 20,
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 17fed1846847..c93ffc5e6e1f 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -16,6 +16,13 @@
 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
 #define PCIE_T_PVPERL_MS		100
 
+/*
+ * End of conventional reset (PERST# de-asserted) to first configuration
+ * request (device able to respond with a "Request Retry Status" completion),
+ * from PCI Express Base Specification r6.0, section 6.6.1.
+ */
+#define PCIE_T_RRS_READY_MS	100
+
 /*
  * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
  * Recommends 1ms to 10ms timeout to check L2 ready.
-- 
2.44.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Damien Le Moal <dlemoal@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Heiko Stuebner <heiko@sntech.de>,
	linux-pci@vger.kernel.org
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/2] PCI: rockchip-host: Wait 100ms after reset before starting configuration
Date: Sat, 13 Apr 2024 09:41:20 +0900	[thread overview]
Message-ID: <20240413004120.1099089-3-dlemoal@kernel.org> (raw)
In-Reply-To: <20240413004120.1099089-1-dlemoal@kernel.org>

The PCI Express Base Specification r6.0, section 6.6.1, states that the
host should wait for at least 100 msec from the end of a conventional
reset (PERST# is de-asserted) before sending a configuration request to
ensure that the device is able to respond with a "Request Retry Status"
completion.

Add the PCIE_T_RRS_READY_MS macro to define this wait time and modify
rockchip_pcie_host_init_port() to add this 100ms sleep after deasserting
PERST# using the ep_gpio GPIO.

Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
---
 drivers/pci/controller/pcie-rockchip-host.c | 2 ++
 drivers/pci/pci.h                           | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index fc868251e570..cbec71114825 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -325,6 +325,8 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 	msleep(PCIE_T_PVPERL_MS);
 	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
+	msleep(PCIE_T_RRS_READY_MS);
+
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
 				 status, PCIE_LINK_UP(status), 20,
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 17fed1846847..c93ffc5e6e1f 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -16,6 +16,13 @@
 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
 #define PCIE_T_PVPERL_MS		100
 
+/*
+ * End of conventional reset (PERST# de-asserted) to first configuration
+ * request (device able to respond with a "Request Retry Status" completion),
+ * from PCI Express Base Specification r6.0, section 6.6.1.
+ */
+#define PCIE_T_RRS_READY_MS	100
+
 /*
  * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
  * Recommends 1ms to 10ms timeout to check L2 ready.
-- 
2.44.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2024-04-13  0:41 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-13  0:41 [PATCH v4 0/2] rockchip rk3399 port initialization fixes Damien Le Moal
2024-04-13  0:41 ` Damien Le Moal
2024-04-13  0:41 ` Damien Le Moal
2024-04-13  0:41 ` [PATCH v4 1/2] PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling Damien Le Moal
2024-04-13  0:41   ` Damien Le Moal
2024-04-13  0:41   ` Damien Le Moal
2024-04-15  6:48   ` Manivannan Sadhasivam
2024-04-15  6:48     ` Manivannan Sadhasivam
2024-04-15  6:48     ` Manivannan Sadhasivam
2024-04-13  0:41 ` Damien Le Moal [this message]
2024-04-13  0:41   ` [PATCH v4 2/2] PCI: rockchip-host: Wait 100ms after reset before starting configuration Damien Le Moal
2024-04-13  0:41   ` Damien Le Moal
2024-04-15  6:50   ` Manivannan Sadhasivam
2024-04-15  6:50     ` Manivannan Sadhasivam
2024-04-15  6:50     ` Manivannan Sadhasivam
2024-05-15 21:14 ` [PATCH v4 0/2] rockchip rk3399 port initialization fixes Bjorn Helgaas
2024-05-15 21:14   ` Bjorn Helgaas
2024-05-15 21:14   ` Bjorn Helgaas
2024-05-17 11:19 ` Krzysztof Wilczyński
2024-05-17 11:19   ` Krzysztof Wilczyński
2024-05-17 11:19   ` Krzysztof Wilczyński

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