All of lore.kernel.org
 help / color / mirror / Atom feed
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org,
	Palmer Dabbelt <palmer@rivosinc.com>,
	 linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev,  linux-doc@vger.kernel.org,
	linux-kselftest@vger.kernel.org,
	 Charlie Jenkins <charlie@rivosinc.com>,
	Heiko Stuebner <heiko@sntech.de>,
	 Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v2 10/17] RISC-V: define the elements of the VCSR vector CSR
Date: Mon, 15 Apr 2024 21:12:07 -0700	[thread overview]
Message-ID: <20240415-dev-charlie-support_thead_vector_6_9-v2-10-c7d68c603268@rivosinc.com> (raw)
In-Reply-To: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com>

From: Heiko Stuebner <heiko@sntech.de>

The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].

Define constants for those to access the elements in a readable way.

Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..13bc99c995d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -215,6 +215,11 @@
 #define SMSTATEEN0_SSTATEEN0_SHIFT	63
 #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
 
+/* VCSR flags */
+#define VCSR_VXRM_MASK			3
+#define VCSR_VXRM_SHIFT			1
+#define VCSR_VXSAT_MASK			1
+
 /* symbolic CSR names: */
 #define CSR_CYCLE		0xc00
 #define CSR_TIME		0xc01

-- 
2.44.0


WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org,
	Palmer Dabbelt <palmer@rivosinc.com>,
	 linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev,  linux-doc@vger.kernel.org,
	linux-kselftest@vger.kernel.org,
	 Charlie Jenkins <charlie@rivosinc.com>,
	Heiko Stuebner <heiko@sntech.de>,
	 Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v2 10/17] RISC-V: define the elements of the VCSR vector CSR
Date: Mon, 15 Apr 2024 21:12:07 -0700	[thread overview]
Message-ID: <20240415-dev-charlie-support_thead_vector_6_9-v2-10-c7d68c603268@rivosinc.com> (raw)
In-Reply-To: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com>

From: Heiko Stuebner <heiko@sntech.de>

The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].

Define constants for those to access the elements in a readable way.

Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..13bc99c995d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -215,6 +215,11 @@
 #define SMSTATEEN0_SSTATEEN0_SHIFT	63
 #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
 
+/* VCSR flags */
+#define VCSR_VXRM_MASK			3
+#define VCSR_VXRM_SHIFT			1
+#define VCSR_VXSAT_MASK			1
+
 /* symbolic CSR names: */
 #define CSR_CYCLE		0xc00
 #define CSR_TIME		0xc01

-- 
2.44.0


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org,
	Palmer Dabbelt <palmer@rivosinc.com>,
	 linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev,  linux-doc@vger.kernel.org,
	linux-kselftest@vger.kernel.org,
	 Charlie Jenkins <charlie@rivosinc.com>,
	Heiko Stuebner <heiko@sntech.de>,
	 Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v2 10/17] RISC-V: define the elements of the VCSR vector CSR
Date: Mon, 15 Apr 2024 21:12:07 -0700	[thread overview]
Message-ID: <20240415-dev-charlie-support_thead_vector_6_9-v2-10-c7d68c603268@rivosinc.com> (raw)
In-Reply-To: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com>

From: Heiko Stuebner <heiko@sntech.de>

The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].

Define constants for those to access the elements in a readable way.

Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..13bc99c995d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -215,6 +215,11 @@
 #define SMSTATEEN0_SSTATEEN0_SHIFT	63
 #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
 
+/* VCSR flags */
+#define VCSR_VXRM_MASK			3
+#define VCSR_VXRM_SHIFT			1
+#define VCSR_VXSAT_MASK			1
+
 /* symbolic CSR names: */
 #define CSR_CYCLE		0xc00
 #define CSR_TIME		0xc01

-- 
2.44.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2024-04-16  4:12 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-16  4:11 [PATCH v2 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-16  4:11 ` Charlie Jenkins
2024-04-16  4:11 ` Charlie Jenkins
2024-04-16  4:11 ` [PATCH v2 01/17] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-16  4:11   ` Charlie Jenkins
2024-04-16  4:11   ` Charlie Jenkins
2024-04-16 15:03   ` Conor Dooley
2024-04-16 15:03     ` Conor Dooley
2024-04-16 15:03     ` Conor Dooley
2024-04-16 20:40     ` Charlie Jenkins
2024-04-16 20:40       ` Charlie Jenkins
2024-04-16 20:40       ` Charlie Jenkins
2024-04-16  4:11 ` [PATCH v2 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-16  4:11   ` Charlie Jenkins
2024-04-16  4:11   ` Charlie Jenkins
2024-04-16 15:16   ` Conor Dooley
2024-04-16 15:16     ` Conor Dooley
2024-04-16 15:16     ` Conor Dooley
2024-04-16 20:43     ` Charlie Jenkins
2024-04-16 20:43       ` Charlie Jenkins
2024-04-16 20:43       ` Charlie Jenkins
2024-04-16 21:10       ` Conor Dooley
2024-04-16 21:10         ` Conor Dooley
2024-04-16 21:10         ` Conor Dooley
2024-04-17 22:51         ` Charlie Jenkins
2024-04-17 22:51           ` Charlie Jenkins
2024-04-17 22:51           ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 03/17] dt-bindings: riscv: Add vendorid Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16 15:05   ` Conor Dooley
2024-04-16 15:05     ` Conor Dooley
2024-04-16 15:05     ` Conor Dooley
2024-04-16  4:12 ` [PATCH v2 04/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16 15:28   ` Conor Dooley
2024-04-16 15:28     ` Conor Dooley
2024-04-16 15:28     ` Conor Dooley
2024-04-16 20:39     ` Charlie Jenkins
2024-04-16 20:39       ` Charlie Jenkins
2024-04-16 20:39       ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 05/17] riscv: Fix extension subset checking Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 06/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-17 13:42   ` Conor Dooley
2024-04-17 13:42     ` Conor Dooley
2024-04-17 13:42     ` Conor Dooley
2024-04-16  4:12 ` [PATCH v2 07/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 08/17] riscv: drivers: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 09/17] riscv: uaccess: Add alternative for xtheadvector uaccess Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` Charlie Jenkins [this message]
2024-04-16  4:12   ` [PATCH v2 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 12/17] riscv: Create xtheadvector file Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-17 14:50   ` Conor Dooley
2024-04-17 14:50     ` Conor Dooley
2024-04-17 14:50     ` Conor Dooley
2024-04-17 22:00     ` Charlie Jenkins
2024-04-17 22:00       ` Charlie Jenkins
2024-04-17 22:00       ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 14/17] riscv: hwprobe: Add vendor extension probing Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 15/17] riscv: hwprobe: Document vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12 ` [PATCH v2 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16  4:12   ` Charlie Jenkins
2024-04-16 15:39 ` [PATCH v2 00/17] riscv: Support vendor extensions and xtheadvector Conor Dooley
2024-04-16 15:39   ` Conor Dooley
2024-04-16 15:39   ` Conor Dooley
2024-04-17 13:17 ` Conor Dooley
2024-04-17 13:17   ` Conor Dooley
2024-04-17 13:17   ` Conor Dooley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240415-dev-charlie-support_thead_vector_6_9-v2-10-c7d68c603268@rivosinc.com \
    --to=charlie@rivosinc.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=cleger@rivosinc.com \
    --cc=conor+dt@kernel.org \
    --cc=conor.dooley@microchip.com \
    --cc=conor@kernel.org \
    --cc=corbet@lwn.net \
    --cc=devicetree@vger.kernel.org \
    --cc=evan@rivosinc.com \
    --cc=guoren@kernel.org \
    --cc=heiko@sntech.de \
    --cc=jernej.skrabec@gmail.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-kselftest@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=palmer@dabbelt.com \
    --cc=palmer@rivosinc.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh@kernel.org \
    --cc=samuel@sholland.org \
    --cc=shuah@kernel.org \
    --cc=wens@csie.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.