From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Clint Taylor <Clinton.A.Taylor@intel.com>,
Gustavo Sousa <gustavo.sousa@intel.com>,
Jani Nikula <jani.nikula@linux.intel.com>
Subject: [PATCH v3 08/21] drm/i915/xe2hpd: Add new C20 PHY SRAM address
Date: Mon, 15 Apr 2024 13:44:10 +0530 [thread overview]
Message-ID: <20240415081423.495834-9-balasubramani.vivekanandan@intel.com> (raw)
In-Reply-To: <20240415081423.495834-1-balasubramani.vivekanandan@intel.com>
Xe2_HPD has different offsets for C20 PHY SRAM configuration context
location. Use the display version to select the right address.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so make sure it is the only display using them in the
driver.
v2:
* Redesigned how the right offsets are selected for different display
IP versions.
Bspec: 67610
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 65 ++++++++++++-------
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 59 ++++++++++++++---
2 files changed, 92 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 33a612892d94..9bf882b439f4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2161,6 +2161,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
bool cntx;
intel_wakeref_t wakeref;
int i;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2170,42 +2171,50 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
/* Read Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
- pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i));
+ pll_state->tx[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_TX_CNTX_CFG(i915, i));
else
- pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i));
+ pll_state->tx[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_TX_CNTX_CFG(i915, i));
}
/* Read common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
- pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i));
+ pll_state->cmn[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_CMN_CNTX_CFG(i915, i));
else
- pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i));
+ pll_state->cmn[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_CMN_CNTX_CFG(i915, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
/* MPLLB configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
- pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i));
+ pll_state->mpllb[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLB_CNTX_CFG(i915, i));
else
- pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i));
+ pll_state->mpllb[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLB_CNTX_CFG(i915, i));
}
} else {
/* MPLLA configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
- pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i));
+ pll_state->mplla[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLA_CNTX_CFG(i915, i));
else
- pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i));
+ pll_state->mplla[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLA_CNTX_CFG(i915, i));
}
}
@@ -2363,17 +2372,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
/* 3.1 Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_A_TX_CNTX_CFG(i915, i),
+ pll_state->tx[i]);
else
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_B_TX_CNTX_CFG(i915, i),
+ pll_state->tx[i]);
}
/* 3.2 common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_A_CMN_CNTX_CFG(i915, i),
+ pll_state->cmn[i]);
else
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_B_CMN_CNTX_CFG(i915, i),
+ pll_state->cmn[i]);
}
/* 3.3 mpllb or mplla configuration */
@@ -2381,22 +2398,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i),
+ PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
pll_state->mpllb[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i),
+ PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
pll_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i),
+ PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
pll_state->mplla[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i),
+ PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
pll_state->mplla[i]);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bdd0c8c4ef97..23a79e911972 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -254,24 +254,67 @@
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
-#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
-#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
+
+#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_A_TX_CNTX_CFG_ADDR : MTL_C20_A_TX_CNTX_CFG_ADDR) - \
+ (idx))
+#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_B_TX_CNTX_CFG_ADDR : MTL_C20_B_TX_CNTX_CFG_ADDR) - \
+ (idx))
#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
-#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
-#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
-#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
-#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
+#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_A_CMN_CNTX_CFG_ADDR : MTL_C20_A_CMN_CNTX_CFG_ADDR) - \
+ (idx))
+#define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_B_CMN_CNTX_CFG_ADDR : MTL_C20_B_CMN_CNTX_CFG_ADDR) - \
+ (idx))
+#define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_A_MPLLA_CFG_ADDR : MTL_C20_A_MPLLA_CFG_ADDR) - \
+ (idx))
+#define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_B_MPLLA_CFG_ADDR : MTL_C20_B_MPLLA_CFG_ADDR) - \
+ (idx))
#define C20_MPLLA_FRACEN REG_BIT(14)
#define C20_FB_CLK_DIV4_EN REG_BIT(13)
#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
-#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
-#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
+#define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_A_MPLLB_CFG_ADDR : MTL_C20_A_MPLLB_CFG_ADDR) - \
+ (idx))
+#define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \
+ (((DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) ? \
+ XE2HPD_C20_B_MPLLB_CFG_ADDR : MTL_C20_B_MPLLB_CFG_ADDR) - \
+ (idx))
#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
#define C20_MPLLB_FRACEN REG_BIT(13)
#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
#define C20_PHY_USE_MPLLB REG_BIT(7)
+#define MTL_C20_A_TX_CNTX_CFG_ADDR 0xCF2E
+#define MTL_C20_B_TX_CNTX_CFG_ADDR 0xCF2A
+#define MTL_C20_A_CMN_CNTX_CFG_ADDR 0xCDAA
+#define MTL_C20_B_CMN_CNTX_CFG_ADDR 0xCDA5
+#define MTL_C20_A_MPLLA_CFG_ADDR 0xCCF0
+#define MTL_C20_B_MPLLA_CFG_ADDR 0xCCE5
+#define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A
+#define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E
+
+#define XE2HPD_C20_A_TX_CNTX_CFG_ADDR 0xCF5E
+#define XE2HPD_C20_B_TX_CNTX_CFG_ADDR 0xCF5A
+#define XE2HPD_C20_A_CMN_CNTX_CFG_ADDR 0xCE8E
+#define XE2HPD_C20_B_CMN_CNTX_CFG_ADDR 0xCE89
+#define XE2HPD_C20_A_MPLLA_CFG_ADDR 0xCE58
+#define XE2HPD_C20_B_MPLLA_CFG_ADDR 0xCE4D
+#define XE2HPD_C20_A_MPLLB_CFG_ADDR 0xCCC2
+#define XE2HPD_C20_B_MPLLB_CFG_ADDR 0xCCB6
+
/* C20 Phy VSwing Masks */
#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
--
2.25.1
next prev parent reply other threads:[~2024-04-15 8:14 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 8:14 [PATCH v3 00/21] Enable display support for Battlemage Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 01/21] drm/xe/display: Lane reversal requires writes to both context lanes Balasubramani Vivekanandan
2024-04-15 15:05 ` Matt Roper
2024-04-15 8:14 ` [PATCH v3 02/21] drm/i915/display: Enable RM timeout detection Balasubramani Vivekanandan
2024-04-15 15:49 ` Matt Roper
2024-04-15 8:14 ` [PATCH v3 03/21] drm/i915/bmg: Define IS_BATTLEMAGE macro Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 04/21] drm/i915/xe2hpd: Skip CCS modifiers Balasubramani Vivekanandan
2024-04-15 16:06 ` Matt Roper
2024-04-16 11:15 ` Juha-Pekka Heikkila
2024-04-15 8:14 ` [PATCH v3 05/21] drm/i915/xe2hpd: Initial cdclk table Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 06/21] drm/i915/bmg: Extend DG2 tc check to future Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 07/21] drm/i915/xe2hpd: Properly disable power in port A Balasubramani Vivekanandan
2024-04-15 8:14 ` Balasubramani Vivekanandan [this message]
2024-04-15 15:32 ` [PATCH v3 08/21] drm/i915/xe2hpd: Add new C20 PHY SRAM address Jani Nikula
2024-04-15 8:14 ` [PATCH v3 09/21] drm/i915/xe2hpd: Add support for eDP PLL configuration Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 10/21] drm/i915/xe2hpd: update pll values in sync with Bspec Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 11/21] drm/i915/xe2hpd: Add display info Balasubramani Vivekanandan
2024-04-15 16:22 ` Matt Roper
2024-04-15 8:14 ` [PATCH v3 12/21] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 13/21] drm/i915/xe2hpd: Add max memory bandwidth algorithm Balasubramani Vivekanandan
2024-04-15 19:52 ` Sripada, Radhakrishna
2024-04-15 8:14 ` [PATCH v3 14/21] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Balasubramani Vivekanandan
2024-04-15 16:25 ` Matt Roper
2024-04-15 8:14 ` [PATCH v3 15/21] drm/i915/bmg: BMG should re-use MTL's south display logic Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 16/21] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 17/21] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 18/21] drm/xe/gt_print: add xe_gt_err_once() Balasubramani Vivekanandan
2024-04-15 8:14 ` [PATCH v3 19/21] drm/xe/device: implement transient flush Balasubramani Vivekanandan
2024-04-15 17:00 ` Matt Roper
2024-04-15 8:14 ` [PATCH v3 20/21] drm/i915/display: perform " Balasubramani Vivekanandan
2024-04-15 17:07 ` Matt Roper
2024-04-15 18:14 ` Matt Roper
2024-04-16 7:40 ` Matthew Auld
2024-04-15 20:55 ` Nirmoy Das
2024-04-15 8:14 ` [PATCH v3 21/21] drm/xe/bmg: Enable the display support Balasubramani Vivekanandan
2024-04-15 19:43 ` ✓ CI.Patch_applied: success for Enable display support for Battlemage Patchwork
2024-04-15 19:43 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-15 19:44 ` ✓ CI.KUnit: success " Patchwork
2024-04-15 19:56 ` ✓ CI.Build: " Patchwork
2024-04-15 19:58 ` ✓ CI.Hooks: " Patchwork
2024-04-15 20:00 ` ✗ CI.checksparse: warning " Patchwork
2024-04-15 20:25 ` ✓ CI.BAT: success " Patchwork
2024-04-15 20:58 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2024-04-15 20:58 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-15 21:14 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-16 8:31 ` ✓ Fi.CI.IGT: " Patchwork
2024-04-16 9:37 ` ✓ CI.FULL: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240415081423.495834-9-balasubramani.vivekanandan@intel.com \
--to=balasubramani.vivekanandan@intel.com \
--cc=Clinton.A.Taylor@intel.com \
--cc=gustavo.sousa@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jani.nikula@linux.intel.com \
--cc=lucas.demarchi@intel.com \
--cc=matthew.d.roper@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.