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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Robert Moore" <robert.moore@intel.com>,
	"Haibo1 Xu" <haibo1.xu@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Andrei Warkentin" <andrei.warkentin@intel.com>,
	"Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v4 10/20] RISC-V: ACPI: Initialize GSI mapping structures
Date: Mon, 15 Apr 2024 22:31:03 +0530	[thread overview]
Message-ID: <20240415170113.662318-11-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240415170113.662318-1-sunilvl@ventanamicro.com>

RISC-V has PLIC and APLIC in MADT as well as namespace devices.
Initialize the list of those structures using MADT and namespace devices
to create mapping between the ACPI handle and the GSI ranges. This is
will be used later to add dependencies.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 arch/riscv/include/asm/irq.h |  22 +++++
 drivers/acpi/riscv/init.c    |   2 +
 drivers/acpi/riscv/init.h    |   4 +
 drivers/acpi/riscv/irq.c     | 159 +++++++++++++++++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 drivers/acpi/riscv/init.h

diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index 8e10a94430a2..44a0b128c602 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
 
 struct fwnode_handle *riscv_get_intc_hwnode(void);
 
+#ifdef CONFIG_ACPI
+
+enum riscv_irqchip_type {
+	ACPI_RISCV_IRQCHIP_INTC		= 0x00,
+	ACPI_RISCV_IRQCHIP_IMSIC	= 0x01,
+	ACPI_RISCV_IRQCHIP_PLIC		= 0x02,
+	ACPI_RISCV_IRQCHIP_APLIC	= 0x03,
+};
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs);
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi);
+
+#else
+static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+					  u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	return 0;
+}
+
+#endif /* CONFIG_ACPI */
+
 #endif /* _ASM_RISCV_IRQ_H */
diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c
index b5807bbdb171..56780af6ceb3 100644
--- a/drivers/acpi/riscv/init.c
+++ b/drivers/acpi/riscv/init.c
@@ -6,7 +6,9 @@
  */
 
 #include <linux/acpi.h>
+#include "init.h"
 
 void __init acpi_riscv_init(void)
 {
+	riscv_acpi_init_gsi_mapping();
 }
diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h
new file mode 100644
index 000000000000..2a488ec684b9
--- /dev/null
+++ b/drivers/acpi/riscv/init.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/init.h>
+
+int __init riscv_acpi_init_gsi_mapping(void);
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
index 36e0525b3235..de0f1ba92068 100644
--- a/drivers/acpi/riscv/irq.c
+++ b/drivers/acpi/riscv/irq.c
@@ -7,6 +7,21 @@
 
 #include <linux/acpi.h>
 #include <linux/sort.h>
+#include <linux/irq.h>
+
+#include "init.h"
+
+struct riscv_ext_intc_list {
+	acpi_handle handle;
+	u32 gsi_base;
+	u32 nr_irqs;
+	u32 nr_idcs;
+	u32 id;
+	u32 type;
+	struct list_head list;
+};
+
+LIST_HEAD(ext_intc_list);
 
 static int irqchip_cmp_func(const void *in0, const void *in1)
 {
@@ -30,3 +45,147 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
 		return;
 	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
 }
+
+static int riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi_base == ext_intc_element->gsi_base) {
+			ext_intc_element->handle = handle;
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs))
+			return ext_intc_element->handle;
+	}
+
+	return NULL;
+}
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (ext_intc_element->handle == ACPI_HANDLE_FWNODE(fwnode)) {
+			*gsi_base = ext_intc_element->gsi_base;
+			*id = ext_intc_element->id;
+			*nr_irqs = ext_intc_element->nr_irqs;
+			if (nr_idcs)
+				*nr_idcs = ext_intc_element->nr_idcs;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct acpi_device *adev;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) {
+			adev = acpi_fetch_acpi_dev(ext_intc_element->handle);
+			if (!adev)
+				return NULL;
+
+			return acpi_fwnode_handle(adev);
+		}
+	}
+
+	return NULL;
+}
+
+static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs,
+					       u32 id, u32 type)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+
+	ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL);
+	if (!ext_intc_element)
+		return -1;
+
+	ext_intc_element->gsi_base = gsi_base;
+	ext_intc_element->nr_irqs = nr_irqs;
+	ext_intc_element->nr_idcs = nr_idcs;
+	ext_intc_element->id = id;
+	list_add_tail(&ext_intc_element->list, &ext_intc_list);
+	return 0;
+}
+
+static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u32 level,
+						    void *context, void **return_value)
+{
+	acpi_status status;
+	u64 gbase;
+
+	if (!acpi_has_method(handle, "_GSB"))
+		return AE_OK;
+
+	status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to evaluate _GSB method\n");
+		return AE_OK;
+	}
+
+	riscv_acpi_update_gsi_handle((u32)gbase, handle);
+	return AE_OK;
+}
+
+static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers *header,
+					      const unsigned long end)
+{
+	struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header;
+
+	riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources,
+				     aplic->num_idcs, aplic->id, ACPI_RISCV_IRQCHIP_APLIC);
+	return 0;
+}
+
+static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *header,
+					     const unsigned long end)
+{
+	struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header;
+
+	riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0,
+				     plic->id, ACPI_RISCV_IRQCHIP_PLIC);
+	return 0;
+}
+
+int __init riscv_acpi_init_gsi_mapping(void)
+{
+	int count = 0;
+
+	count = acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt, 0);
+	if (count <= 0) {
+		acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_madt, 0);
+		acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL);
+		return 0;
+	}
+
+	acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL);
+	return 0;
+}
-- 
2.40.1


WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	acpica-devel@lists.linux.dev
Cc: "Marc Zyngier" <maz@kernel.org>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Haibo1 Xu" <haibo1.xu@intel.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Robert Moore" <robert.moore@intel.com>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Andrei Warkentin" <andrei.warkentin@intel.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Will Deacon" <will@kernel.org>, "Len Brown" <lenb@kernel.org>
Subject: [RFC PATCH v4 10/20] RISC-V: ACPI: Initialize GSI mapping structures
Date: Mon, 15 Apr 2024 22:31:03 +0530	[thread overview]
Message-ID: <20240415170113.662318-11-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240415170113.662318-1-sunilvl@ventanamicro.com>

RISC-V has PLIC and APLIC in MADT as well as namespace devices.
Initialize the list of those structures using MADT and namespace devices
to create mapping between the ACPI handle and the GSI ranges. This is
will be used later to add dependencies.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 arch/riscv/include/asm/irq.h |  22 +++++
 drivers/acpi/riscv/init.c    |   2 +
 drivers/acpi/riscv/init.h    |   4 +
 drivers/acpi/riscv/irq.c     | 159 +++++++++++++++++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 drivers/acpi/riscv/init.h

diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index 8e10a94430a2..44a0b128c602 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
 
 struct fwnode_handle *riscv_get_intc_hwnode(void);
 
+#ifdef CONFIG_ACPI
+
+enum riscv_irqchip_type {
+	ACPI_RISCV_IRQCHIP_INTC		= 0x00,
+	ACPI_RISCV_IRQCHIP_IMSIC	= 0x01,
+	ACPI_RISCV_IRQCHIP_PLIC		= 0x02,
+	ACPI_RISCV_IRQCHIP_APLIC	= 0x03,
+};
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs);
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi);
+
+#else
+static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+					  u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	return 0;
+}
+
+#endif /* CONFIG_ACPI */
+
 #endif /* _ASM_RISCV_IRQ_H */
diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c
index b5807bbdb171..56780af6ceb3 100644
--- a/drivers/acpi/riscv/init.c
+++ b/drivers/acpi/riscv/init.c
@@ -6,7 +6,9 @@
  */
 
 #include <linux/acpi.h>
+#include "init.h"
 
 void __init acpi_riscv_init(void)
 {
+	riscv_acpi_init_gsi_mapping();
 }
diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h
new file mode 100644
index 000000000000..2a488ec684b9
--- /dev/null
+++ b/drivers/acpi/riscv/init.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/init.h>
+
+int __init riscv_acpi_init_gsi_mapping(void);
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
index 36e0525b3235..de0f1ba92068 100644
--- a/drivers/acpi/riscv/irq.c
+++ b/drivers/acpi/riscv/irq.c
@@ -7,6 +7,21 @@
 
 #include <linux/acpi.h>
 #include <linux/sort.h>
+#include <linux/irq.h>
+
+#include "init.h"
+
+struct riscv_ext_intc_list {
+	acpi_handle handle;
+	u32 gsi_base;
+	u32 nr_irqs;
+	u32 nr_idcs;
+	u32 id;
+	u32 type;
+	struct list_head list;
+};
+
+LIST_HEAD(ext_intc_list);
 
 static int irqchip_cmp_func(const void *in0, const void *in1)
 {
@@ -30,3 +45,147 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
 		return;
 	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
 }
+
+static int riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi_base == ext_intc_element->gsi_base) {
+			ext_intc_element->handle = handle;
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs))
+			return ext_intc_element->handle;
+	}
+
+	return NULL;
+}
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (ext_intc_element->handle == ACPI_HANDLE_FWNODE(fwnode)) {
+			*gsi_base = ext_intc_element->gsi_base;
+			*id = ext_intc_element->id;
+			*nr_irqs = ext_intc_element->nr_irqs;
+			if (nr_idcs)
+				*nr_idcs = ext_intc_element->nr_idcs;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct acpi_device *adev;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) {
+			adev = acpi_fetch_acpi_dev(ext_intc_element->handle);
+			if (!adev)
+				return NULL;
+
+			return acpi_fwnode_handle(adev);
+		}
+	}
+
+	return NULL;
+}
+
+static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs,
+					       u32 id, u32 type)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+
+	ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL);
+	if (!ext_intc_element)
+		return -1;
+
+	ext_intc_element->gsi_base = gsi_base;
+	ext_intc_element->nr_irqs = nr_irqs;
+	ext_intc_element->nr_idcs = nr_idcs;
+	ext_intc_element->id = id;
+	list_add_tail(&ext_intc_element->list, &ext_intc_list);
+	return 0;
+}
+
+static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u32 level,
+						    void *context, void **return_value)
+{
+	acpi_status status;
+	u64 gbase;
+
+	if (!acpi_has_method(handle, "_GSB"))
+		return AE_OK;
+
+	status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to evaluate _GSB method\n");
+		return AE_OK;
+	}
+
+	riscv_acpi_update_gsi_handle((u32)gbase, handle);
+	return AE_OK;
+}
+
+static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers *header,
+					      const unsigned long end)
+{
+	struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header;
+
+	riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources,
+				     aplic->num_idcs, aplic->id, ACPI_RISCV_IRQCHIP_APLIC);
+	return 0;
+}
+
+static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *header,
+					     const unsigned long end)
+{
+	struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header;
+
+	riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0,
+				     plic->id, ACPI_RISCV_IRQCHIP_PLIC);
+	return 0;
+}
+
+int __init riscv_acpi_init_gsi_mapping(void)
+{
+	int count = 0;
+
+	count = acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt, 0);
+	if (count <= 0) {
+		acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_madt, 0);
+		acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL);
+		return 0;
+	}
+
+	acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL);
+	return 0;
+}
-- 
2.40.1


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WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Robert Moore" <robert.moore@intel.com>,
	"Haibo1 Xu" <haibo1.xu@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Andrei Warkentin" <andrei.warkentin@intel.com>,
	"Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v4 10/20] RISC-V: ACPI: Initialize GSI mapping structures
Date: Mon, 15 Apr 2024 22:31:03 +0530	[thread overview]
Message-ID: <20240415170113.662318-11-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240415170113.662318-1-sunilvl@ventanamicro.com>

RISC-V has PLIC and APLIC in MADT as well as namespace devices.
Initialize the list of those structures using MADT and namespace devices
to create mapping between the ACPI handle and the GSI ranges. This is
will be used later to add dependencies.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 arch/riscv/include/asm/irq.h |  22 +++++
 drivers/acpi/riscv/init.c    |   2 +
 drivers/acpi/riscv/init.h    |   4 +
 drivers/acpi/riscv/irq.c     | 159 +++++++++++++++++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 drivers/acpi/riscv/init.h

diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index 8e10a94430a2..44a0b128c602 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
 
 struct fwnode_handle *riscv_get_intc_hwnode(void);
 
+#ifdef CONFIG_ACPI
+
+enum riscv_irqchip_type {
+	ACPI_RISCV_IRQCHIP_INTC		= 0x00,
+	ACPI_RISCV_IRQCHIP_IMSIC	= 0x01,
+	ACPI_RISCV_IRQCHIP_PLIC		= 0x02,
+	ACPI_RISCV_IRQCHIP_APLIC	= 0x03,
+};
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs);
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi);
+
+#else
+static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+					  u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	return 0;
+}
+
+#endif /* CONFIG_ACPI */
+
 #endif /* _ASM_RISCV_IRQ_H */
diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c
index b5807bbdb171..56780af6ceb3 100644
--- a/drivers/acpi/riscv/init.c
+++ b/drivers/acpi/riscv/init.c
@@ -6,7 +6,9 @@
  */
 
 #include <linux/acpi.h>
+#include "init.h"
 
 void __init acpi_riscv_init(void)
 {
+	riscv_acpi_init_gsi_mapping();
 }
diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h
new file mode 100644
index 000000000000..2a488ec684b9
--- /dev/null
+++ b/drivers/acpi/riscv/init.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/init.h>
+
+int __init riscv_acpi_init_gsi_mapping(void);
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
index 36e0525b3235..de0f1ba92068 100644
--- a/drivers/acpi/riscv/irq.c
+++ b/drivers/acpi/riscv/irq.c
@@ -7,6 +7,21 @@
 
 #include <linux/acpi.h>
 #include <linux/sort.h>
+#include <linux/irq.h>
+
+#include "init.h"
+
+struct riscv_ext_intc_list {
+	acpi_handle handle;
+	u32 gsi_base;
+	u32 nr_irqs;
+	u32 nr_idcs;
+	u32 id;
+	u32 type;
+	struct list_head list;
+};
+
+LIST_HEAD(ext_intc_list);
 
 static int irqchip_cmp_func(const void *in0, const void *in1)
 {
@@ -30,3 +45,147 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
 		return;
 	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
 }
+
+static int riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi_base == ext_intc_element->gsi_base) {
+			ext_intc_element->handle = handle;
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs))
+			return ext_intc_element->handle;
+	}
+
+	return NULL;
+}
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (ext_intc_element->handle == ACPI_HANDLE_FWNODE(fwnode)) {
+			*gsi_base = ext_intc_element->gsi_base;
+			*id = ext_intc_element->id;
+			*nr_irqs = ext_intc_element->nr_irqs;
+			if (nr_idcs)
+				*nr_idcs = ext_intc_element->nr_idcs;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct acpi_device *adev;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) {
+			adev = acpi_fetch_acpi_dev(ext_intc_element->handle);
+			if (!adev)
+				return NULL;
+
+			return acpi_fwnode_handle(adev);
+		}
+	}
+
+	return NULL;
+}
+
+static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs,
+					       u32 id, u32 type)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+
+	ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL);
+	if (!ext_intc_element)
+		return -1;
+
+	ext_intc_element->gsi_base = gsi_base;
+	ext_intc_element->nr_irqs = nr_irqs;
+	ext_intc_element->nr_idcs = nr_idcs;
+	ext_intc_element->id = id;
+	list_add_tail(&ext_intc_element->list, &ext_intc_list);
+	return 0;
+}
+
+static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u32 level,
+						    void *context, void **return_value)
+{
+	acpi_status status;
+	u64 gbase;
+
+	if (!acpi_has_method(handle, "_GSB"))
+		return AE_OK;
+
+	status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to evaluate _GSB method\n");
+		return AE_OK;
+	}
+
+	riscv_acpi_update_gsi_handle((u32)gbase, handle);
+	return AE_OK;
+}
+
+static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers *header,
+					      const unsigned long end)
+{
+	struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header;
+
+	riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources,
+				     aplic->num_idcs, aplic->id, ACPI_RISCV_IRQCHIP_APLIC);
+	return 0;
+}
+
+static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *header,
+					     const unsigned long end)
+{
+	struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header;
+
+	riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0,
+				     plic->id, ACPI_RISCV_IRQCHIP_PLIC);
+	return 0;
+}
+
+int __init riscv_acpi_init_gsi_mapping(void)
+{
+	int count = 0;
+
+	count = acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt, 0);
+	if (count <= 0) {
+		acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_madt, 0);
+		acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL);
+		return 0;
+	}
+
+	acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL);
+	return 0;
+}
-- 
2.40.1


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  parent reply	other threads:[~2024-04-15 17:02 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-15 17:00 [RFC PATCH v4 00/20] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-04-15 17:00 ` Sunil V L
2024-04-15 17:00 ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 01/20] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 02/20] RISC-V: ACPI: Implement PCI related functionality Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 03/20] PCI: Make pci_create_root_bus() declare its reliance on MSI domains Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 23:15   ` Bjorn Helgaas
2024-04-15 23:15     ` Bjorn Helgaas
2024-04-15 23:15     ` Bjorn Helgaas
2024-04-16  8:24     ` Sunil V L
2024-04-16  8:24       ` Sunil V L
2024-04-16  8:24       ` Sunil V L
2024-04-16 20:46       ` Bjorn Helgaas
2024-04-16 20:46         ` Bjorn Helgaas
2024-04-16 20:46         ` Bjorn Helgaas
2024-04-17 15:33         ` Sunil V L
2024-04-17 15:33           ` Sunil V L
2024-04-17 15:33           ` Sunil V L
2024-04-18 11:45           ` Sunil V L
2024-04-18 11:45             ` Sunil V L
2024-04-18 11:45             ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 04/20] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 05/20] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 06/20] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:00   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 07/20] RISC-V: Kconfig: Select deferred GSI probe for ACPI systems Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 08/20] ACPI: scan: Refactor dependency creation Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 09/20] drivers/acpi/scan.c: Update _DEP honor list Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` Sunil V L [this message]
2024-04-15 17:01   ` [RFC PATCH v4 10/20] RISC-V: ACPI: Initialize GSI mapping structures Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 11/20] ACPI: scan.c: Define weak function to populate dependencies Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 12/20] RISC-V: ACPI: Implement function to add implicit dependencies Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 13/20] ACPI/PNP: Initialize PNP devices skipped due to _DEP Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 14/20] irqchip: riscv-intc: Add ACPI support for AIA Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 15/20] irqchip: riscv-imsic: Add ACPI support Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 16/20] irqchip: riscv-aplic: " Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 17/20] irqchip: irq-sifive-plic: " Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 18/20] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 19/20] irqchip: riscv-intc: Set ACPI irqmodel Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 20/20] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-15 17:01   ` Sunil V L
2024-04-18 13:49 ` [RFC PATCH v4 00/20] RISC-V: ACPI: Add external interrupt controller support Björn Töpel
2024-04-18 13:49   ` Björn Töpel
2024-04-18 13:49   ` Björn Töpel
2024-04-18 13:58   ` Sunil V L
2024-04-18 13:58     ` Sunil V L
2024-04-18 13:58     ` Sunil V L
2024-04-18 14:20     ` Heinrich Schuchardt
2024-04-18 14:20       ` Heinrich Schuchardt
2024-04-18 14:20       ` Heinrich Schuchardt
2024-04-22 19:28 ` Rafael J. Wysocki
2024-04-22 19:28   ` Rafael J. Wysocki
2024-04-22 19:28   ` Rafael J. Wysocki
2024-04-24 17:55   ` Björn Töpel
2024-04-24 17:55     ` Björn Töpel
2024-04-24 17:55     ` Björn Töpel
2024-04-29  6:41     ` Sunil V L
2024-04-29  6:41       ` Sunil V L
2024-04-29  6:41       ` Sunil V L

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