From: Alexandru Gagniuc <mr.nuke.me@gmail.com> To: "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Vinod Koul" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org Cc: Alexandru Gagniuc <mr.nuke.me@gmail.com> Subject: [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Date: Mon, 15 Apr 2024 13:20:47 -0500 [thread overview] Message-ID: <20240415182052.374494-3-mr.nuke.me@gmail.com> (raw) In-Reply-To: <20240415182052.374494-1-mr.nuke.me@gmail.com> The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> --- drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0a3f846695b8..c748d2f124f3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x28044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x28044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { @@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { @@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie2_pipe_clk = { + .halt_reg = 0x2a044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2a044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie2_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie2_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { @@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie3_pipe_clk = { + .halt_reg = 0x2b044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2b044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie3_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie3_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(100000000, P_GPLL0, 8, 0, 0), @@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { -- 2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Gagniuc <mr.nuke.me@gmail.com> To: "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Vinod Koul" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org Cc: Alexandru Gagniuc <mr.nuke.me@gmail.com> Subject: [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Date: Mon, 15 Apr 2024 13:20:47 -0500 [thread overview] Message-ID: <20240415182052.374494-3-mr.nuke.me@gmail.com> (raw) In-Reply-To: <20240415182052.374494-1-mr.nuke.me@gmail.com> The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> --- drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0a3f846695b8..c748d2f124f3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x28044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x28044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { @@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { @@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie2_pipe_clk = { + .halt_reg = 0x2a044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2a044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie2_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie2_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { @@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie3_pipe_clk = { + .halt_reg = 0x2b044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2b044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie3_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie3_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(100000000, P_GPLL0, 8, 0, 0), @@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { -- 2.40.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2024-04-15 18:21 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-15 18:20 [PATCH v3 0/7] ipq9574: Enable PCI-Express support Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-15 18:20 ` [PATCH v3 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc [this message] 2024-04-15 18:20 ` [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Alexandru Gagniuc 2024-04-15 20:04 ` Dmitry Baryshkov 2024-04-15 20:04 ` Dmitry Baryshkov 2024-04-19 22:22 ` Stephen Boyd 2024-04-19 22:22 ` Stephen Boyd 2024-04-15 18:20 ` [PATCH v3 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-18 12:59 ` Rob Herring 2024-04-18 12:59 ` Rob Herring 2024-04-15 18:20 ` [PATCH v3 4/7] PCI: qcom: Add support for IPQ9574 Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-15 20:04 ` Dmitry Baryshkov 2024-04-15 20:04 ` Dmitry Baryshkov 2024-04-15 20:07 ` mr.nuke.me 2024-04-15 20:07 ` mr.nuke.me 2024-04-17 7:06 ` Manivannan Sadhasivam 2024-04-17 7:06 ` Manivannan Sadhasivam 2024-04-19 19:44 ` mr.nuke.me 2024-04-19 19:44 ` mr.nuke.me 2024-04-22 7:11 ` Manivannan Sadhasivam 2024-04-22 7:11 ` Manivannan Sadhasivam 2024-04-17 7:14 ` Manivannan Sadhasivam 2024-04-17 7:14 ` Manivannan Sadhasivam 2024-04-15 18:20 ` [PATCH v3 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-18 13:00 ` Rob Herring 2024-04-18 13:00 ` Rob Herring 2024-04-15 18:20 ` [PATCH v3 6/7] phy: qcom-qmp-pcie: add support for " Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-15 20:10 ` Dmitry Baryshkov 2024-04-15 20:10 ` Dmitry Baryshkov 2024-04-15 21:25 ` mr.nuke.me 2024-04-15 21:25 ` mr.nuke.me 2024-04-16 21:25 ` Alex G. 2024-04-16 21:25 ` Alex G. 2024-04-16 21:50 ` Dmitry Baryshkov 2024-04-16 21:50 ` Dmitry Baryshkov 2024-04-29 6:20 ` Varadarajan Narayanan 2024-04-29 6:20 ` Varadarajan Narayanan 2024-04-29 10:55 ` Dmitry Baryshkov 2024-04-29 10:55 ` Dmitry Baryshkov 2024-04-30 6:31 ` Varadarajan Narayanan 2024-04-30 6:31 ` Varadarajan Narayanan 2024-04-30 21:51 ` mr.nuke.me 2024-04-30 21:51 ` mr.nuke.me 2024-04-30 21:59 ` Dmitry Baryshkov 2024-04-30 21:59 ` Dmitry Baryshkov 2024-04-15 18:20 ` [PATCH v3 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Alexandru Gagniuc 2024-04-15 18:20 ` Alexandru Gagniuc 2024-04-17 7:34 ` Manivannan Sadhasivam 2024-04-17 7:34 ` Manivannan Sadhasivam 2024-04-18 15:33 ` mr.nuke.me 2024-04-18 15:33 ` mr.nuke.me 2024-04-22 7:10 ` Manivannan Sadhasivam 2024-04-22 7:10 ` Manivannan Sadhasivam 2024-04-22 14:29 ` Konrad Dybcio 2024-04-22 14:29 ` Konrad Dybcio 2024-04-19 14:28 ` [PATCH v3 0/7] ipq9574: Enable PCI-Express support Kathiravan Thirumoorthy 2024-04-19 14:28 ` Kathiravan Thirumoorthy 2024-04-19 19:47 ` mr.nuke.me 2024-04-19 19:47 ` mr.nuke.me 2024-04-23 6:11 ` Kathiravan Thirumoorthy 2024-04-23 6:11 ` Kathiravan Thirumoorthy
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