From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Anup Patel <anup@brainfault.org>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 16/24] RISC-V: KVM: Improve firmware counter read function Date: Tue, 16 Apr 2024 11:44:13 -0700 [thread overview] Message-ID: <20240416184421.3693802-17-atishp@rivosinc.com> (raw) In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 55861b5d3382..fa0f535bbbf0 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -89,7 +89,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba unsigned long ctr_mask, unsigned long flags, unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata); -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index e1409ec9afc0..04db1f993c47 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -235,6 +235,11 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, u64 enabled, running; int fevent_code; + if (cidx >= kvm_pmu_num_counters(kvpmu) || cidx == 1) { + pr_warn("Invalid counter id [%ld] during read\n", cidx); + return -EINVAL; + } + pmc = &kvpmu->pmc[cidx]; if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) { @@ -747,7 +752,7 @@ int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, return 0; } -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { int ret; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index cf111de51bdb..e4be34e03e83 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -62,7 +62,7 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, ret = kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ: - ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); + ret = kvm_riscv_vcpu_pmu_fw_ctr_read(vcpu, cp->a0, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ_HI: if (IS_ENABLED(CONFIG_32BIT)) -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Anup Patel <anup@brainfault.org>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 16/24] RISC-V: KVM: Improve firmware counter read function Date: Tue, 16 Apr 2024 11:44:13 -0700 [thread overview] Message-ID: <20240416184421.3693802-17-atishp@rivosinc.com> (raw) In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 55861b5d3382..fa0f535bbbf0 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -89,7 +89,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba unsigned long ctr_mask, unsigned long flags, unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata); -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index e1409ec9afc0..04db1f993c47 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -235,6 +235,11 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, u64 enabled, running; int fevent_code; + if (cidx >= kvm_pmu_num_counters(kvpmu) || cidx == 1) { + pr_warn("Invalid counter id [%ld] during read\n", cidx); + return -EINVAL; + } + pmc = &kvpmu->pmc[cidx]; if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) { @@ -747,7 +752,7 @@ int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, return 0; } -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { int ret; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index cf111de51bdb..e4be34e03e83 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -62,7 +62,7 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, ret = kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ: - ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); + ret = kvm_riscv_vcpu_pmu_fw_ctr_read(vcpu, cp->a0, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ_HI: if (IS_ENABLED(CONFIG_32BIT)) -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-16 18:45 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-16 18:43 [PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:43 ` [PATCH v7 01/24] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:43 ` [PATCH v7 02/24] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 03/24] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 04/24] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 05/24] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 07/24] RISC-V: Use the minor version mask while computing sbi version Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 08/24] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-17 4:02 ` Samuel Holland 2024-04-17 4:02 ` Samuel Holland 2024-04-18 7:47 ` Atish Patra 2024-04-18 7:47 ` Atish Patra 2024-04-18 20:01 ` Samuel Holland 2024-04-18 20:01 ` Samuel Holland 2024-04-19 23:42 ` Atish Kumar Patra 2024-04-19 23:42 ` Atish Kumar Patra 2024-04-16 18:44 ` [PATCH v7 09/24] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 10/24] RISC-V: KVM: Fix the initial sample period value Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 11/24] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 12/24] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 14/24] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` Atish Patra [this message] 2024-04-16 18:44 ` [PATCH v7 16/24] RISC-V: KVM: Improve firmware counter read function Atish Patra 2024-04-16 18:44 ` [PATCH v7 17/24] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 18/24] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 21/24] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 23/24] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 20:54 ` [PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Palmer Dabbelt 2024-04-16 20:54 ` Palmer Dabbelt
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