From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: "Atish Patra" <atishp@rivosinc.com>, "Clément Léger" <cleger@rivosinc.com>, "Conor Dooley" <conor.dooley@microchip.com>, "Anup Patel" <anup@brainfault.org>, "Andrew Jones" <ajones@ventanamicro.com>, "Ajay Kaher" <ajay.kaher@broadcom.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alexghiti@rivosinc.com>, "Juergen Gross" <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, "Mark Rutland" <mark.rutland@arm.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Shuah Khan" <shuah@kernel.org>, virtualization@lists.linux.dev, "Will Deacon" <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 01/24] RISC-V: Fix the typo in Scountovf CSR name Date: Tue, 16 Apr 2024 11:43:58 -0700 [thread overview] Message-ID: <20240416184421.3693802-2-atishp@rivosinc.com> (raw) In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/csr.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..9d1b07932794 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8cbe6e5f9c39..3e44d2fb8bf8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,7 +27,7 @@ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: "Atish Patra" <atishp@rivosinc.com>, "Clément Léger" <cleger@rivosinc.com>, "Conor Dooley" <conor.dooley@microchip.com>, "Anup Patel" <anup@brainfault.org>, "Andrew Jones" <ajones@ventanamicro.com>, "Ajay Kaher" <ajay.kaher@broadcom.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alexghiti@rivosinc.com>, "Juergen Gross" <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, "Mark Rutland" <mark.rutland@arm.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Shuah Khan" <shuah@kernel.org>, virtualization@lists.linux.dev, "Will Deacon" <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 01/24] RISC-V: Fix the typo in Scountovf CSR name Date: Tue, 16 Apr 2024 11:43:58 -0700 [thread overview] Message-ID: <20240416184421.3693802-2-atishp@rivosinc.com> (raw) In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/csr.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..9d1b07932794 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8cbe6e5f9c39..3e44d2fb8bf8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,7 +27,7 @@ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \ -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-16 18:44 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-16 18:43 [PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:43 ` Atish Patra [this message] 2024-04-16 18:43 ` [PATCH v7 01/24] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-04-16 18:43 ` [PATCH v7 02/24] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 03/24] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 04/24] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 05/24] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 07/24] RISC-V: Use the minor version mask while computing sbi version Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 08/24] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-17 4:02 ` Samuel Holland 2024-04-17 4:02 ` Samuel Holland 2024-04-18 7:47 ` Atish Patra 2024-04-18 7:47 ` Atish Patra 2024-04-18 20:01 ` Samuel Holland 2024-04-18 20:01 ` Samuel Holland 2024-04-19 23:42 ` Atish Kumar Patra 2024-04-19 23:42 ` Atish Kumar Patra 2024-04-16 18:44 ` [PATCH v7 09/24] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 10/24] RISC-V: KVM: Fix the initial sample period value Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 11/24] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 12/24] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 14/24] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 16/24] RISC-V: KVM: Improve firmware counter read function Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 17/24] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 18/24] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 21/24] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 23/24] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 20:54 ` [PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Palmer Dabbelt 2024-04-16 20:54 ` Palmer Dabbelt
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