From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Palmer Dabbelt <palmer@rivosinc.com>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 05/24] RISC-V: Add SBI PMU snapshot definitions Date: Tue, 16 Apr 2024 11:44:02 -0700 [thread overview] Message-ID: <20240416184421.3693802-6-atishp@rivosinc.com> (raw) In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4afa2cd01bae..9aada4b9f7b5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET BIT(0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 extern unsigned long sbi_spec_version; struct sbiret { -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Palmer Dabbelt <palmer@rivosinc.com>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 05/24] RISC-V: Add SBI PMU snapshot definitions Date: Tue, 16 Apr 2024 11:44:02 -0700 [thread overview] Message-ID: <20240416184421.3693802-6-atishp@rivosinc.com> (raw) In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4afa2cd01bae..9aada4b9f7b5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET BIT(0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 extern unsigned long sbi_spec_version; struct sbiret { -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-16 18:44 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-16 18:43 [PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:43 ` [PATCH v7 01/24] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:43 ` [PATCH v7 02/24] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-04-16 18:43 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 03/24] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 04/24] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` Atish Patra [this message] 2024-04-16 18:44 ` [PATCH v7 05/24] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-04-16 18:44 ` [PATCH v7 06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 07/24] RISC-V: Use the minor version mask while computing sbi version Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 08/24] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-17 4:02 ` Samuel Holland 2024-04-17 4:02 ` Samuel Holland 2024-04-18 7:47 ` Atish Patra 2024-04-18 7:47 ` Atish Patra 2024-04-18 20:01 ` Samuel Holland 2024-04-18 20:01 ` Samuel Holland 2024-04-19 23:42 ` Atish Kumar Patra 2024-04-19 23:42 ` Atish Kumar Patra 2024-04-16 18:44 ` [PATCH v7 09/24] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 10/24] RISC-V: KVM: Fix the initial sample period value Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 11/24] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 12/24] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 14/24] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 16/24] RISC-V: KVM: Improve firmware counter read function Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 17/24] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 18/24] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 21/24] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 23/24] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 18:44 ` [PATCH v7 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test Atish Patra 2024-04-16 18:44 ` Atish Patra 2024-04-16 20:54 ` [PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Palmer Dabbelt 2024-04-16 20:54 ` Palmer Dabbelt
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