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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: [PATCH v2 05/11] drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL
Date: Wed, 17 Apr 2024 01:10:04 +0300	[thread overview]
Message-ID: <20240416221010.376865-6-imre.deak@intel.com> (raw)
In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com>

The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.

Bspec: 49259

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 0448cc343a33f..847e264e5bb8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
 					  struct intel_crtc_state *crtc_state,
 					  bool dsc)
 {
-	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
+	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) {
 		int output_bpp = bpp;
 		int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock);
 		/*
-- 
2.43.3


  parent reply	other threads:[~2024-04-16 22:09 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-16 22:09 [PATCH v2 00/11] drm/i915/dp: Few MTL/DSC and a UHBR monitor fix Imre Deak
2024-04-16 22:10 ` [PATCH v2 01/11] drm/i915/dp: Fix DSC line buffer depth programming Imre Deak
2024-04-16 22:10 ` [PATCH v2 02/11] drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit Imre Deak
2024-04-16 22:10 ` [PATCH v2 03/11] drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp Imre Deak
2024-04-16 22:10 ` [PATCH v2 04/11] drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit Imre Deak
2024-04-17 12:42   ` Nautiyal, Ankit K
2024-04-16 22:10 ` Imre Deak [this message]
2024-04-16 22:10 ` [PATCH v2 06/11] drm/i915/dp_mst: Sanitize calculating " Imre Deak
2024-04-16 22:10 ` [PATCH v2 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported() Imre Deak
2024-04-17  9:21   ` Jani Nikula
2024-04-17 11:49     ` Imre Deak
2024-04-17 14:19   ` [PATCH v3 07/11] drm/dp: Add drm_dp_128b132b_supported() Imre Deak
2024-04-16 22:10 ` [PATCH v2 08/11] drm/dp_mst: Factor out drm_dp_mst_port_is_logical() Imre Deak
2024-04-16 22:10 ` [PATCH v2 09/11] drm/dp_mst: Add drm_dp_mst_aux_for_parent() Imre Deak
2024-04-16 22:10 ` [PATCH v2 10/11] drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports Imre Deak
2024-04-16 22:10 ` [PATCH v2 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates Imre Deak
2024-04-17  9:39   ` Jani Nikula
2024-04-17 11:46     ` Imre Deak
2024-04-17 14:22   ` [PATCH v3 " Imre Deak
2024-04-16 22:44 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev2) Patchwork
2024-04-16 22:44 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-16 22:51 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-17  6:20 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-04-17 16:34 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4) Patchwork
2024-04-17 16:34 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-17 16:43 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-18 12:22 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-04-19 14:45   ` Imre Deak
2024-04-24 12:41     ` Illipilli, TejasreeX
2024-04-24  6:52 ` ✓ Fi.CI.IGT: success " Patchwork

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