From: Georgi Djakov <quic_c_gdjako@quicinc.com> To: <will@kernel.org>, <robin.murphy@arm.com>, <joro@8bytes.org>, <iommu@lists.linux.dev> Cc: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <devicetree@vger.kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robdclark@gmail.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>, <quic_cgoldswo@quicinc.com>, <quic_sukadev@quicinc.com>, <quic_pdaly@quicinc.com>, <quic_sudaraja@quicinc.com>, <djakov@kernel.org> Subject: [PATCH v8 5/7] arm64: dts: qcom: sdm845: Add DT nodes for the TBUs Date: Wed, 17 Apr 2024 06:37:29 -0700 [thread overview] Message-ID: <20240417133731.2055383-6-quic_c_gdjako@quicinc.com> (raw) In-Reply-To: <20240417133731.2055383-1-quic_c_gdjako@quicinc.com> Add the device-tree nodes for the TBUs (translation buffer units) that are present on the sdm845 platforms. The TBUs can be used debug the kernel and provide additional information when a context faults occur. Describe the all registers, clocks, interconnects and power-domain resources that are needed for each of the TBUs. Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f20be99ee7e..fa9403aad96f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -5085,6 +5086,78 @@ apps_smmu: iommu@15000000 { <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; + anoc_1_tbu: tbu@150c5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c5000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x0 0x400>; + }; + + anoc_2_tbu: tbu@150c9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x400 0x400>; + }; + + mnoc_hf_0_tbu: tbu@150cd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150cd000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x800 0x400>; + }; + + mnoc_hf_1_tbu: tbu@150d1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d1000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; + }; + + mnoc_sf_0_tbu: tbu@150d5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d5000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; + }; + + compute_dsp_tbu: tbu@150d9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; + }; + + adsp_tbu: tbu@150dd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150dd000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; + }; + + anoc_1_pcie_tbu: tbu@150e1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150e1000 0x0 0x1000>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; + }; + lpasscc: clock-controller@17014000 { compatible = "qcom,sdm845-lpasscc"; reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
WARNING: multiple messages have this Message-ID (diff)
From: Georgi Djakov <quic_c_gdjako@quicinc.com> To: <will@kernel.org>, <robin.murphy@arm.com>, <joro@8bytes.org>, <iommu@lists.linux.dev> Cc: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <devicetree@vger.kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robdclark@gmail.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>, <quic_cgoldswo@quicinc.com>, <quic_sukadev@quicinc.com>, <quic_pdaly@quicinc.com>, <quic_sudaraja@quicinc.com>, <djakov@kernel.org> Subject: [PATCH v8 5/7] arm64: dts: qcom: sdm845: Add DT nodes for the TBUs Date: Wed, 17 Apr 2024 06:37:29 -0700 [thread overview] Message-ID: <20240417133731.2055383-6-quic_c_gdjako@quicinc.com> (raw) In-Reply-To: <20240417133731.2055383-1-quic_c_gdjako@quicinc.com> Add the device-tree nodes for the TBUs (translation buffer units) that are present on the sdm845 platforms. The TBUs can be used debug the kernel and provide additional information when a context faults occur. Describe the all registers, clocks, interconnects and power-domain resources that are needed for each of the TBUs. Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f20be99ee7e..fa9403aad96f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -5085,6 +5086,78 @@ apps_smmu: iommu@15000000 { <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; + anoc_1_tbu: tbu@150c5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c5000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x0 0x400>; + }; + + anoc_2_tbu: tbu@150c9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x400 0x400>; + }; + + mnoc_hf_0_tbu: tbu@150cd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150cd000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x800 0x400>; + }; + + mnoc_hf_1_tbu: tbu@150d1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d1000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; + }; + + mnoc_sf_0_tbu: tbu@150d5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d5000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; + }; + + compute_dsp_tbu: tbu@150d9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; + }; + + adsp_tbu: tbu@150dd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150dd000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; + }; + + anoc_1_pcie_tbu: tbu@150e1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150e1000 0x0 0x1000>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; + }; + lpasscc: clock-controller@17014000 { compatible = "qcom,sdm845-lpasscc"; reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-17 13:38 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-17 13:37 [PATCH v8 0/7] Add support for Translation Buffer Units Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-04-17 13:37 ` [PATCH v8 1/7] dt-bindings: iommu: Add Qualcomm TBU Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-04-17 13:37 ` [PATCH v8 2/7] iommu/arm-smmu-qcom-debug: Add support for TBUs Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-05-01 14:34 ` Will Deacon 2024-05-01 14:34 ` Will Deacon 2024-05-02 16:53 ` Georgi Djakov 2024-05-02 16:53 ` Georgi Djakov 2024-04-17 13:37 ` [PATCH v8 3/7] iommu/arm-smmu: Allow using a threaded handler for context interrupts Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-04-17 13:37 ` [PATCH v8 4/7] iommu/arm-smmu-qcom: Use a custom context fault handler for sdm845 Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov [this message] 2024-04-17 13:37 ` [PATCH v8 5/7] arm64: dts: qcom: sdm845: Add DT nodes for the TBUs Georgi Djakov 2024-04-17 13:37 ` [PATCH v8 6/7] iommu/arm-smmu-qcom: Use the custom fault handler on more platforms Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-04-17 13:37 ` [PATCH v8 7/7] arm64: dts: qcom: sc7280: Add DT nodes for the TBUs Georgi Djakov 2024-04-17 13:37 ` Georgi Djakov 2024-04-19 15:33 ` [PATCH v8 0/7] Add support for Translation Buffer Units Will Deacon 2024-04-19 15:33 ` Will Deacon
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