From: "Clément Léger" <cleger@rivosinc.com> To: Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org> Cc: "Clément Léger" <cleger@rivosinc.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, "Ved Shanbhogue" <ved@rivosinc.com> Subject: [RFC PATCH 3/7] riscv: add Ssdbltrp ISA extension parsing Date: Thu, 18 Apr 2024 16:26:42 +0200 [thread overview] Message-ID: <20240418142701.1493091-4-cleger@rivosinc.com> (raw) In-Reply-To: <20240418142701.1493091-1-cleger@rivosinc.com> Handle Ssdbltrp extension at isa parsing level. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..5528159b3d5d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -102,6 +102,7 @@ #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +#define EXC_DOUBLE_TRAP 16 #define EXC_INST_GUEST_PAGE_FAULT 20 #define EXC_LOAD_GUEST_PAGE_FAULT 21 #define EXC_VIRTUAL_INST_FAULT 22 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5340f818746b..16d2ad7ca9b2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,7 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_SSDBLTRP 74 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..5cff21adf2c4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(ssdbltrp, RISCV_ISA_EXT_SSDBLTRP), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), -- 2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: "Clément Léger" <cleger@rivosinc.com> To: Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org> Cc: "Clément Léger" <cleger@rivosinc.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, "Ved Shanbhogue" <ved@rivosinc.com> Subject: [RFC PATCH 3/7] riscv: add Ssdbltrp ISA extension parsing Date: Thu, 18 Apr 2024 16:26:42 +0200 [thread overview] Message-ID: <20240418142701.1493091-4-cleger@rivosinc.com> (raw) In-Reply-To: <20240418142701.1493091-1-cleger@rivosinc.com> Handle Ssdbltrp extension at isa parsing level. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..5528159b3d5d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -102,6 +102,7 @@ #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +#define EXC_DOUBLE_TRAP 16 #define EXC_INST_GUEST_PAGE_FAULT 20 #define EXC_LOAD_GUEST_PAGE_FAULT 21 #define EXC_VIRTUAL_INST_FAULT 22 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5340f818746b..16d2ad7ca9b2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,7 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_SSDBLTRP 74 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..5cff21adf2c4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(ssdbltrp, RISCV_ISA_EXT_SSDBLTRP), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-18 14:27 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-18 14:26 [RFC PATCH 0/7] riscv: Add support for Ssdbltrp extension Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-18 14:26 ` [RFC PATCH 1/7] riscv: kvm: add support for FWFT SBI extension Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-26 23:44 ` Deepak Gupta 2024-04-26 23:44 ` Deepak Gupta 2024-04-30 7:26 ` Clément Léger 2024-04-30 7:26 ` Clément Léger 2024-04-18 14:26 ` [RFC PATCH 2/7] dt-bindings: riscv: add Ssdbltrp ISA extension description Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-23 16:30 ` Conor Dooley 2024-04-23 16:30 ` Conor Dooley 2024-04-24 7:20 ` Clément Léger 2024-04-24 7:20 ` Clément Léger 2024-04-24 7:40 ` Conor Dooley 2024-04-24 7:40 ` Conor Dooley 2024-04-24 21:38 ` Ved Shanbhogue 2024-04-24 21:38 ` Ved Shanbhogue 2024-04-18 14:26 ` Clément Léger [this message] 2024-04-18 14:26 ` [RFC PATCH 3/7] riscv: add Ssdbltrp ISA extension parsing Clément Léger 2024-04-18 14:26 ` [RFC PATCH 4/7] riscv: handle Ssdbltrp mstatus SDT bit Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-18 14:26 ` [RFC PATCH 5/7] riscv: add double trap driver Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-23 16:39 ` Conor Dooley 2024-04-23 16:39 ` Conor Dooley 2024-04-24 8:56 ` Clément Léger 2024-04-24 8:56 ` Clément Léger 2024-04-26 23:59 ` Deepak Gupta 2024-04-26 23:59 ` Deepak Gupta 2024-05-14 8:06 ` Clément Léger 2024-05-14 8:06 ` Clément Léger 2024-05-14 14:38 ` Deepak Gupta 2024-05-14 14:38 ` Deepak Gupta 2024-04-18 14:26 ` [RFC PATCH 6/7] riscv: kvm: add SBI FWFT support for SBI_FWFT_DOUBLE_TRAP_ENABLE Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-27 1:17 ` Deepak Gupta 2024-04-27 1:17 ` Deepak Gupta 2024-04-27 15:36 ` Deepak Gupta 2024-04-27 15:36 ` Deepak Gupta 2024-05-14 9:43 ` Clément Léger 2024-05-14 9:43 ` Clément Léger 2024-05-14 16:05 ` Deepak Gupta 2024-05-14 16:05 ` Deepak Gupta 2024-04-18 14:26 ` [RFC PATCH 7/7] RISC-V: KVM: add support for double trap exception Clément Léger 2024-04-18 14:26 ` Clément Léger 2024-04-27 1:33 ` Deepak Gupta 2024-04-27 1:33 ` Deepak Gupta 2024-04-30 15:35 ` Clément Léger 2024-04-30 15:35 ` Clément Léger 2024-04-23 16:24 ` [RFC PATCH 0/7] riscv: Add support for Ssdbltrp extension Conor Dooley 2024-04-23 16:24 ` Conor Dooley 2024-04-24 7:23 ` Clément Léger 2024-04-24 7:23 ` Clément Léger
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