All of lore.kernel.org
 help / color / mirror / Atom feed
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Robert Moore" <robert.moore@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Andrei Warkentin" <andrei.warkentin@intel.com>,
	"Haibo1 Xu" <haibo1.xu@intel.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [PATCH v5 09/17] ACPI: RISC-V: Implement PCI related functionality
Date: Wed,  1 May 2024 17:47:34 +0530	[thread overview]
Message-ID: <20240501121742.1215792-10-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com>

Replace the dummy implementation for PCI related functions with actual
implementation. This needs ECAM and MCFG CONFIG options to be enabled
for RISC-V.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 arch/riscv/Kconfig       |  2 ++
 arch/riscv/kernel/acpi.c | 31 ++++++++++++++-----------------
 drivers/pci/pci-acpi.c   |  2 +-
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f7a36d79ff1a..09a86256ddfa 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -13,6 +13,7 @@ config 32BIT
 config RISCV
 	def_bool y
 	select ACPI_GENERIC_GSI if ACPI
+	select ACPI_MCFG if (ACPI && PCI)
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 	select ARCH_ACPI_DEFERRED_GSI if ACPI
 	select ARCH_DMA_DEFAULT_COHERENT
@@ -176,6 +177,7 @@ config RISCV
 	select OF_EARLY_FLATTREE
 	select OF_IRQ
 	select PCI_DOMAINS_GENERIC if PCI
+	select PCI_ECAM if (ACPI && PCI)
 	select PCI_MSI if PCI
 	select RISCV_ALTERNATIVE if !XIP_KERNEL
 	select RISCV_APLIC
diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
index e619edc8b0cc..41aa77c8484b 100644
--- a/arch/riscv/kernel/acpi.c
+++ b/arch/riscv/kernel/acpi.c
@@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 #ifdef CONFIG_PCI
 
 /*
- * These interfaces are defined just to enable building ACPI core.
- * TODO: Update it with actual implementation when external interrupt
- * controller support is added in RISC-V ACPI.
+ * raw_pci_read/write - Platform-specific PCI config space access.
  */
-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
-		 int reg, int len, u32 *val)
+int raw_pci_read(unsigned int domain, unsigned int bus,
+		 unsigned int devfn, int reg, int len, u32 *val)
 {
-	return PCIBIOS_DEVICE_NOT_FOUND;
-}
+	struct pci_bus *b = pci_find_bus(domain, bus);
 
-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
-		  int reg, int len, u32 val)
-{
-	return PCIBIOS_DEVICE_NOT_FOUND;
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->read(b, devfn, reg, len, val);
 }
 
-int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
+int raw_pci_write(unsigned int domain, unsigned int bus,
+		  unsigned int devfn, int reg, int len, u32 val)
 {
-	return -1;
-}
+	struct pci_bus *b = pci_find_bus(domain, bus);
 
-struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
-{
-	return NULL;
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->write(b, devfn, reg, len, val);
 }
+
 #endif	/* CONFIG_PCI */
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index e8d84fa435da..b5892d0fa68c 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void)
 }
 arch_initcall(acpi_pci_init);
 
-#if defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 
 /*
  * Try to assign the IRQ number when probing a new device
-- 
2.40.1


WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev
Cc: "Rafael J . Wysocki" <rafael@kernel.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Haibo1 Xu" <haibo1.xu@intel.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Robert Moore" <robert.moore@intel.com>,
	"Andrei Warkentin" <andrei.warkentin@intel.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Anup Patel" <anup@brainfault.org>, "Len Brown" <lenb@kernel.org>
Subject: [PATCH v5 09/17] ACPI: RISC-V: Implement PCI related functionality
Date: Wed,  1 May 2024 17:47:34 +0530	[thread overview]
Message-ID: <20240501121742.1215792-10-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com>

Replace the dummy implementation for PCI related functions with actual
implementation. This needs ECAM and MCFG CONFIG options to be enabled
for RISC-V.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 arch/riscv/Kconfig       |  2 ++
 arch/riscv/kernel/acpi.c | 31 ++++++++++++++-----------------
 drivers/pci/pci-acpi.c   |  2 +-
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f7a36d79ff1a..09a86256ddfa 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -13,6 +13,7 @@ config 32BIT
 config RISCV
 	def_bool y
 	select ACPI_GENERIC_GSI if ACPI
+	select ACPI_MCFG if (ACPI && PCI)
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 	select ARCH_ACPI_DEFERRED_GSI if ACPI
 	select ARCH_DMA_DEFAULT_COHERENT
@@ -176,6 +177,7 @@ config RISCV
 	select OF_EARLY_FLATTREE
 	select OF_IRQ
 	select PCI_DOMAINS_GENERIC if PCI
+	select PCI_ECAM if (ACPI && PCI)
 	select PCI_MSI if PCI
 	select RISCV_ALTERNATIVE if !XIP_KERNEL
 	select RISCV_APLIC
diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
index e619edc8b0cc..41aa77c8484b 100644
--- a/arch/riscv/kernel/acpi.c
+++ b/arch/riscv/kernel/acpi.c
@@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 #ifdef CONFIG_PCI
 
 /*
- * These interfaces are defined just to enable building ACPI core.
- * TODO: Update it with actual implementation when external interrupt
- * controller support is added in RISC-V ACPI.
+ * raw_pci_read/write - Platform-specific PCI config space access.
  */
-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
-		 int reg, int len, u32 *val)
+int raw_pci_read(unsigned int domain, unsigned int bus,
+		 unsigned int devfn, int reg, int len, u32 *val)
 {
-	return PCIBIOS_DEVICE_NOT_FOUND;
-}
+	struct pci_bus *b = pci_find_bus(domain, bus);
 
-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
-		  int reg, int len, u32 val)
-{
-	return PCIBIOS_DEVICE_NOT_FOUND;
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->read(b, devfn, reg, len, val);
 }
 
-int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
+int raw_pci_write(unsigned int domain, unsigned int bus,
+		  unsigned int devfn, int reg, int len, u32 val)
 {
-	return -1;
-}
+	struct pci_bus *b = pci_find_bus(domain, bus);
 
-struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
-{
-	return NULL;
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->write(b, devfn, reg, len, val);
 }
+
 #endif	/* CONFIG_PCI */
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index e8d84fa435da..b5892d0fa68c 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void)
 }
 arch_initcall(acpi_pci_init);
 
-#if defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 
 /*
  * Try to assign the IRQ number when probing a new device
-- 
2.40.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Robert Moore" <robert.moore@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Andrei Warkentin" <andrei.warkentin@intel.com>,
	"Haibo1 Xu" <haibo1.xu@intel.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [PATCH v5 09/17] ACPI: RISC-V: Implement PCI related functionality
Date: Wed,  1 May 2024 17:47:34 +0530	[thread overview]
Message-ID: <20240501121742.1215792-10-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com>

Replace the dummy implementation for PCI related functions with actual
implementation. This needs ECAM and MCFG CONFIG options to be enabled
for RISC-V.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 arch/riscv/Kconfig       |  2 ++
 arch/riscv/kernel/acpi.c | 31 ++++++++++++++-----------------
 drivers/pci/pci-acpi.c   |  2 +-
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f7a36d79ff1a..09a86256ddfa 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -13,6 +13,7 @@ config 32BIT
 config RISCV
 	def_bool y
 	select ACPI_GENERIC_GSI if ACPI
+	select ACPI_MCFG if (ACPI && PCI)
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 	select ARCH_ACPI_DEFERRED_GSI if ACPI
 	select ARCH_DMA_DEFAULT_COHERENT
@@ -176,6 +177,7 @@ config RISCV
 	select OF_EARLY_FLATTREE
 	select OF_IRQ
 	select PCI_DOMAINS_GENERIC if PCI
+	select PCI_ECAM if (ACPI && PCI)
 	select PCI_MSI if PCI
 	select RISCV_ALTERNATIVE if !XIP_KERNEL
 	select RISCV_APLIC
diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
index e619edc8b0cc..41aa77c8484b 100644
--- a/arch/riscv/kernel/acpi.c
+++ b/arch/riscv/kernel/acpi.c
@@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 #ifdef CONFIG_PCI
 
 /*
- * These interfaces are defined just to enable building ACPI core.
- * TODO: Update it with actual implementation when external interrupt
- * controller support is added in RISC-V ACPI.
+ * raw_pci_read/write - Platform-specific PCI config space access.
  */
-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
-		 int reg, int len, u32 *val)
+int raw_pci_read(unsigned int domain, unsigned int bus,
+		 unsigned int devfn, int reg, int len, u32 *val)
 {
-	return PCIBIOS_DEVICE_NOT_FOUND;
-}
+	struct pci_bus *b = pci_find_bus(domain, bus);
 
-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
-		  int reg, int len, u32 val)
-{
-	return PCIBIOS_DEVICE_NOT_FOUND;
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->read(b, devfn, reg, len, val);
 }
 
-int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
+int raw_pci_write(unsigned int domain, unsigned int bus,
+		  unsigned int devfn, int reg, int len, u32 val)
 {
-	return -1;
-}
+	struct pci_bus *b = pci_find_bus(domain, bus);
 
-struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
-{
-	return NULL;
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->write(b, devfn, reg, len, val);
 }
+
 #endif	/* CONFIG_PCI */
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index e8d84fa435da..b5892d0fa68c 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void)
 }
 arch_initcall(acpi_pci_init);
 
-#if defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 
 /*
  * Try to assign the IRQ number when probing a new device
-- 
2.40.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2024-05-01 12:19 UTC|newest]

Thread overview: 138+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-01 12:17 [PATCH v5 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-05-01 12:17 ` Sunil V L
2024-05-01 12:17 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:59   ` Will Deacon
2024-05-01 12:59     ` Will Deacon
2024-05-01 12:59     ` Will Deacon
2024-05-02  9:22   ` Andy Shevchenko
2024-05-02  9:22     ` Andy Shevchenko
2024-05-02  9:22     ` Andy Shevchenko
2024-05-02  9:56     ` Sunil V L
2024-05-02  9:56       ` Sunil V L
2024-05-02  9:56       ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 03/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-02  9:24   ` Andy Shevchenko
2024-05-02  9:24     ` Andy Shevchenko
2024-05-02  9:24     ` Andy Shevchenko
2024-05-02 10:02     ` Sunil V L
2024-05-02 10:02       ` Sunil V L
2024-05-02 10:02       ` Sunil V L
2024-05-02 10:12       ` Sudeep Holla
2024-05-02 10:12         ` Sudeep Holla
2024-05-02 10:12         ` Sudeep Holla
2024-05-02 10:19         ` Andy Shevchenko
2024-05-02 10:19           ` Andy Shevchenko
2024-05-02 10:19           ` Andy Shevchenko
2024-05-02 11:00           ` Sunil V L
2024-05-02 11:00             ` Sunil V L
2024-05-02 11:00             ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-02  9:20   ` Andy Shevchenko
2024-05-02  9:20     ` Andy Shevchenko
2024-05-02  9:20     ` Andy Shevchenko
2024-05-02  9:55     ` Sunil V L
2024-05-02  9:55       ` Sunil V L
2024-05-02  9:55       ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-23 21:59   ` Bjorn Helgaas
2024-05-23 21:59     ` Bjorn Helgaas
2024-05-23 21:59     ` Bjorn Helgaas
2024-05-27  4:35     ` Sunil V L
2024-05-27  4:35       ` Sunil V L
2024-05-27  4:35       ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 16:56   ` Bjorn Helgaas
2024-05-01 16:56     ` Bjorn Helgaas
2024-05-01 16:56     ` Bjorn Helgaas
2024-05-02  9:25     ` Andy Shevchenko
2024-05-02  9:25       ` Andy Shevchenko
2024-05-02  9:25       ` Andy Shevchenko
2024-05-02  9:32       ` Sunil V L
2024-05-02  9:32         ` Sunil V L
2024-05-02  9:32         ` Sunil V L
2024-05-01 12:17 ` Sunil V L [this message]
2024-05-01 12:17   ` [PATCH v5 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-23 21:47   ` Thomas Gleixner
2024-05-23 21:47     ` Thomas Gleixner
2024-05-23 21:47     ` Thomas Gleixner
2024-05-27  4:39     ` Sunil V L
2024-05-27  4:39       ` Sunil V L
2024-05-27  4:39       ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-23 22:00   ` Thomas Gleixner
2024-05-23 22:00     ` Thomas Gleixner
2024-05-23 22:00     ` Thomas Gleixner
2024-05-27  4:52     ` Sunil V L
2024-05-27  4:52       ` Sunil V L
2024-05-27  4:52       ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 15/17] irqchip/riscv-aplic: " Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 16/17] irqchip/sifive-plic: " Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 17/17] serial: 8250: Add 8250_acpi driver Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-01 12:17   ` Sunil V L
2024-05-02  9:17   ` Andy Shevchenko
2024-05-02  9:17     ` Andy Shevchenko
2024-05-02  9:17     ` Andy Shevchenko
2024-05-02  9:50     ` Sunil V L
2024-05-02  9:50       ` Sunil V L
2024-05-02  9:50       ` Sunil V L
2024-05-02 10:09       ` Andy Shevchenko
2024-05-02 10:09         ` Andy Shevchenko
2024-05-02 10:09         ` Andy Shevchenko
2024-05-02 11:20         ` Sunil V L
2024-05-02 11:20           ` Sunil V L
2024-05-02 11:20           ` Sunil V L
2024-05-02 15:35           ` Andy Shevchenko
2024-05-02 15:35             ` Andy Shevchenko
2024-05-02 15:35             ` Andy Shevchenko
2024-05-03 13:59             ` Sunil V L
2024-05-03 13:59               ` Sunil V L
2024-05-03 13:59               ` Sunil V L
2024-05-03 15:32               ` Andy Shevchenko
2024-05-03 15:32                 ` Andy Shevchenko
2024-05-03 15:32                 ` Andy Shevchenko
2024-05-06 11:45                 ` Sunil V L
2024-05-06 11:45                   ` Sunil V L
2024-05-06 11:45                   ` Sunil V L
2024-05-04 15:53   ` Greg Kroah-Hartman
2024-05-04 15:53     ` Greg Kroah-Hartman
2024-05-04 15:53     ` Greg Kroah-Hartman

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240501121742.1215792-10-sunilvl@ventanamicro.com \
    --to=sunilvl@ventanamicro.com \
    --cc=acpica-devel@lists.linux.dev \
    --cc=ajones@ventanamicro.com \
    --cc=andrei.warkentin@intel.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=anup@brainfault.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=atishp@rivosinc.com \
    --cc=bhelgaas@google.com \
    --cc=bjorn@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=conor.dooley@microchip.com \
    --cc=gregkh@linuxfoundation.org \
    --cc=haibo1.xu@intel.com \
    --cc=jirislaby@kernel.org \
    --cc=lenb@kernel.org \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux-serial@vger.kernel.org \
    --cc=maz@kernel.org \
    --cc=paul.walmsley@sifive.com \
    --cc=rafael@kernel.org \
    --cc=robert.moore@intel.com \
    --cc=samuel.holland@sifive.com \
    --cc=tglx@linutronix.de \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.