From: Simon Horman <horms+renesas@verge.net.au>
To: linux-renesas-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
Magnus Damm <magnus.damm@gmail.com>,
Fabrizio Castro <fabrizio.castro@bp.renesas.com>,
Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH 06/44] arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes
Date: Thu, 24 Jan 2019 16:12:00 +0100 [thread overview]
Message-ID: <2660a6af690ebbb4f342944ec8ab7c1a2766672c.1548233325.git.horms+renesas@verge.net.au> (raw)
In-Reply-To: <cover.1548233325.git.horms+renesas@verge.net.au>
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Add the device nodes for all RZ/G2E SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 171 ++++++++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 7b3d247ca004..872efa755532 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -126,6 +126,94 @@
#power-domain-cells = <1>;
};
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b0000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a774c0",
"renesas,rcar-dmac";
@@ -228,6 +316,40 @@
dma-channels = <16>;
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a774c0",
"renesas,rcar-gen3-scif", "renesas,scif";
@@ -242,6 +364,55 @@
status = "disabled";
};
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 64>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms+renesas@verge.net.au>
To: linux-renesas-soc@vger.kernel.org
Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>,
Simon Horman <horms+renesas@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 06/44] arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes
Date: Thu, 24 Jan 2019 16:12:00 +0100 [thread overview]
Message-ID: <2660a6af690ebbb4f342944ec8ab7c1a2766672c.1548233325.git.horms+renesas@verge.net.au> (raw)
In-Reply-To: <cover.1548233325.git.horms+renesas@verge.net.au>
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Add the device nodes for all RZ/G2E SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 171 ++++++++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 7b3d247ca004..872efa755532 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -126,6 +126,94 @@
#power-domain-cells = <1>;
};
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b0000 {
+ compatible = "renesas,hscif-r8a774c0",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a774c0",
"renesas,rcar-dmac";
@@ -228,6 +316,40 @@
dma-channels = <16>;
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a774c0",
"renesas,rcar-gen3-scif", "renesas,scif";
@@ -242,6 +364,55 @@
status = "disabled";
};
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a774c0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 64>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.11.0
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next prev parent reply other threads:[~2019-01-24 15:12 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-24 15:12 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:11 ` [PATCH 01/44] arm64: dts: renesas: r8a77990: ebisu: Add backlight Simon Horman
2019-01-24 15:11 ` Simon Horman
2019-01-24 15:11 ` [PATCH 02/44] arm64: dts: renesas: r8a77995: draak: Set better backlight levels Simon Horman
2019-01-24 15:11 ` Simon Horman
2019-01-24 15:11 ` [PATCH 03/44] arm64: dts: renesas: r8a77990: ebisu: Fix EthernetAVB phy mode to rgmii Simon Horman
2019-01-24 15:11 ` Simon Horman
2019-01-24 15:11 ` [PATCH 04/44] arm64: dts: renesas: Initial device tree for r8a774c0 Simon Horman
2019-01-24 15:11 ` Simon Horman
2019-01-24 15:11 ` [PATCH 05/44] arm64: dts: renesas: r8a774c0: Add SYS-DMAC controller nodes Simon Horman
2019-01-24 15:11 ` Simon Horman
2019-01-24 15:12 ` Simon Horman [this message]
2019-01-24 15:12 ` [PATCH 06/44] arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes Simon Horman
2019-01-24 15:12 ` [PATCH 07/44] arm64: dts: renesas: r8a774c0: Add INTC-EX device node Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 08/44] arm64: dts: renesas: r8a774c0: Add PFC support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 09/44] arm64: dts: renesas: r8a774c0: Add GPIO device nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 10/44] arm64: dts: renesas: r8a774c0: Add Ethernet AVB node Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 11/44] arm64: dts: renesas: r8a774c0: Add watchdog support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 12/44] arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 13/44] arm64: dts: renesas: r8a774c0: Add SDHI nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 14/44] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 15/44] arm64: dts: renesas: r8a774c0: Add IPMMU device nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 16/44] arm64: dts: renesas: r8a774c0: Add CAN nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 17/44] arm64: dts: renesas: r8a774c0: Add thermal support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 18/44] arm64: dts: renesas: r8a774c0: Add MSIOF nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 19/44] arm64: dts: renesas: r8a774c0: Add audio support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 20/44] arm64: dts: renesas: r8a774c0: Add PWM support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 21/44] arm64: dts: renesas: r8a774c0: Add display output support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 22/44] arm64: dts: renesas: r8a774c0: Add USB2.0 phy and host device nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 23/44] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB " Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 24/44] arm64: dts: renesas: r8a774c0: Add USB3.0 " Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 25/44] arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 26/44] arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB " Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 27/44] arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC " Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 28/44] arm64: dts: renesas: r8a774c0: Add PCIe device node Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 29/44] arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 30/44] arm64: dts: renesas: r8a774a1: Fix hsusb reg size Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 31/44] arm64: dts: renesas: r8a77990: sort pciec0 node within soc node Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 32/44] arm64: dts: renesas: r8a77990: Sort i2c nodes " Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 33/44] arm64: dts: renesas: r8a7796: salvator-xs: Convert to new LVDS DT bindings Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 34/44] arm64: dts: renesas: ulcb: use audio-graph-card Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 35/44] arm64: dts: renesas: ulcb: add HDMI sound support Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 36/44] arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 37/44] arm64: dts: renesas: r8a7795: remove BUSIF0 settings from rcar_sound,ssi Simon Horman
2019-01-24 15:12 ` [PATCH 37/44] arm64: dts: renesas: r8a7795: remove BUSIF0 settings from rcar_sound, ssi Simon Horman
2019-01-24 15:12 ` [PATCH 38/44] arm64: dts: renesas: r8a7796: remove BUSIF0 settings from rcar_sound,ssi Simon Horman
2019-01-24 15:12 ` [PATCH 38/44] arm64: dts: renesas: r8a7796: remove BUSIF0 settings from rcar_sound, ssi Simon Horman
2019-01-24 15:12 ` [PATCH 39/44] arm64: dts: renesas: r8a77990-ebisu: use simple-audio-card Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 40/44] arm64: dts: renesas: v3msk: specify EtherAVB PHY IRQ Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 41/44] arm64: dts: renesas: r8a77990: ebisu: Fix backlight regulator numbering Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 42/44] arm64: dts: renesas: r8a774c0: Enable DMA for SCIF2 Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 43/44] arm64: dts: renesas: r8a77990: " Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-24 15:12 ` [PATCH 44/44] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 Simon Horman
2019-01-24 15:12 ` Simon Horman
2019-01-30 16:55 ` [GIT PULL] Renesas ARM64 Based SoC DT Updates for v5.1 Arnd Bergmann
2019-01-30 16:55 ` Arnd Bergmann
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