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From: Michal Simek <michal.simek@xilinx.com>
To: u-boot@lists.denx.de, git@xilinx.com
Cc: Joe Hershberger <joe.hershberger@ni.com>,
	Ramon Fried <rfried.dev@gmail.com>
Subject: [PATCH 1/6] net: zynq_gem: Use shared MDIO bus support for zynqmp
Date: Wed, 30 Mar 2022 11:07:53 +0200	[thread overview]
Message-ID: <337b1a38ba36cde1951739af62fb3d2736d97f53.1648631275.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1648631275.git.michal.simek@xilinx.com>

CONFIG_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
---

 drivers/net/zynq_gem.c | 32 +++++++++++++++++++++++---------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3118d1472669..168aabbdd006 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -33,6 +33,7 @@
 #include <linux/bitops.h>
 #include <linux/err.h>
 #include <linux/errno.h>
+#include <eth_phy.h>
 
 /* Bit/mask specification */
 #define ZYNQ_GEM_PHYMNTNC_OP_MASK	0x40020000 /* operation mask bits */
@@ -321,6 +322,9 @@ static int zynq_phy_init(struct udevice *dev)
 	/* Enable only MDIO bus */
 	writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs_mdio->nwctrl);
 
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		priv->phyaddr = eth_phy_get_addr(dev);
+
 	priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 				   priv->interface);
 	if (!priv->phydev)
@@ -771,14 +775,22 @@ static int zynq_gem_probe(struct udevice *dev)
 		}
 	}
 
-	priv->bus = mdio_alloc();
-	priv->bus->read = zynq_gem_miiphy_read;
-	priv->bus->write = zynq_gem_miiphy_write;
-	priv->bus->priv = priv;
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		priv->bus = eth_phy_get_mdio_bus(dev);
 
-	ret = mdio_register_seq(priv->bus, dev_seq(dev));
-	if (ret)
-		goto err2;
+	if (!priv->bus) {
+		priv->bus = mdio_alloc();
+		priv->bus->read = zynq_gem_miiphy_read;
+		priv->bus->write = zynq_gem_miiphy_write;
+		priv->bus->priv = priv;
+
+		ret = mdio_register_seq(priv->bus, dev_seq(dev));
+		if (ret)
+			goto err2;
+	}
+
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		eth_phy_set_mdio_bus(dev, priv->bus);
 
 	ret = zynq_phy_init(dev);
 	if (ret)
@@ -841,8 +853,10 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
 		ofnode parent;
 
 		debug("phy-handle does exist %s\n", dev->name);
-		priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
-							"reg", -1);
+		if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
+			priv->phyaddr = ofnode_read_u32_default
+					(phandle_args.node, "reg", -1);
+
 		priv->phy_of_node = phandle_args.node;
 		priv->max_speed = ofnode_read_u32_default(phandle_args.node,
 							  "max-speed",
-- 
2.35.1


  reply	other threads:[~2022-03-30  9:08 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-30  9:07 [PATCH 0/6] xilinx: Add support for DM_ETH_PHY Michal Simek
2022-03-30  9:07 ` Michal Simek [this message]
2022-03-30  9:07 ` [PATCH 2/6] net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabled Michal Simek
2022-03-30  9:07 ` [PATCH 3/6] net: zynq_gem: Move ethernet info print statement Michal Simek
2022-03-30  9:07 ` [PATCH 4/6] gpio: slg7xl45106: Update gpio desc flags from DT Michal Simek
2022-03-30  9:07 ` [PATCH 5/6] firmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config api Michal Simek
2022-03-30  9:07 ` [PATCH 6/6] net: zynq_gem: Add SGMII dynamic config support Michal Simek
2022-04-05 13:13 ` [PATCH 0/6] xilinx: Add support for DM_ETH_PHY Michal Simek

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