From: Nicola Vetrini <nicola.vetrini@bugseng.com>
To: xen-devel@lists.xenproject.org
Cc: consulting@bugseng.com,
Nicola Vetrini <nicola.vetrini@bugseng.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>,
Bertrand Marquis <bertrand.marquis@arm.com>,
Michal Orzel <michal.orzel@amd.com>,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
Subject: [XEN PATCH 5/7] xen/arm: traps: add ASSERT_UNREACHABLE() where needed
Date: Mon, 11 Dec 2023 11:30:26 +0100 [thread overview]
Message-ID: <394b69b769f2dc2461d2ddb0c7e037f4794eb244.1702283415.git.nicola.vetrini@bugseng.com> (raw)
In-Reply-To: <cover.1702283415.git.nicola.vetrini@bugseng.com>
The branches of the switch after a call to 'do_unexpected_trap'
cannot return, but there is one path that may return, hence
only some clauses are marked with ASSERT_UNREACHABLE().
Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
---
xen/arch/arm/traps.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 3784e8276ef6..e7c920b043d2 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -2152,7 +2152,7 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs)
case HSR_EC_SVE:
/* An SVE exception is a bug somewhere in hypervisor code */
do_unexpected_trap("SVE trap at EL2", regs);
- break;
+ ASSERT_UNREACHABLE();
#endif
case HSR_EC_DATA_ABORT_CURR_EL:
case HSR_EC_INSTR_ABORT_CURR_EL:
@@ -2171,13 +2171,13 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs)
dump_hyp_walk(get_hfar(is_data));
do_unexpected_trap(fault, regs);
-
- break;
+ ASSERT_UNREACHABLE();
}
default:
printk("Hypervisor Trap. HSR=%#"PRIregister" EC=0x%x IL=%x Syndrome=0x%"PRIx32"\n",
hsr.bits, hsr.ec, hsr.len, hsr.iss);
do_unexpected_trap("Hypervisor", regs);
+ ASSERT_UNREACHABLE();
}
}
--
2.34.1
next prev parent reply other threads:[~2023-12-11 10:30 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-11 10:30 [XEN PATCH 0/7] address violations of MISRA C:2012 Rule 2.1 Nicola Vetrini
2023-12-11 10:30 ` [XEN PATCH 1/7] xen/shutdown: address " Nicola Vetrini
2023-12-12 1:39 ` Stefano Stabellini
2023-12-12 9:45 ` Jan Beulich
2023-12-12 9:53 ` Nicola Vetrini
2023-12-12 10:30 ` Jan Beulich
2023-12-11 10:30 ` [XEN PATCH 2/7] x86/mm: " Nicola Vetrini
2023-12-12 1:42 ` Stefano Stabellini
2023-12-12 9:12 ` Nicola Vetrini
2023-12-12 9:53 ` Jan Beulich
2023-12-13 14:44 ` Nicola Vetrini
2023-12-14 7:57 ` Jan Beulich
2023-12-14 8:52 ` Nicola Vetrini
2023-12-11 10:30 ` [XEN PATCH 3/7] xen/arm: " Nicola Vetrini
2023-12-11 12:29 ` Julien Grall
2023-12-11 13:06 ` Michal Orzel
2023-12-11 14:14 ` Julien Grall
2023-12-11 14:52 ` Nicola Vetrini
2023-12-11 10:30 ` [XEN PATCH 4/7] xen/sched: " Nicola Vetrini
2023-12-11 13:30 ` George Dunlap
2023-12-12 1:43 ` Stefano Stabellini
2023-12-11 10:30 ` Nicola Vetrini [this message]
2023-12-11 12:32 ` [XEN PATCH 5/7] xen/arm: traps: add ASSERT_UNREACHABLE() where needed Julien Grall
2023-12-11 14:54 ` Nicola Vetrini
2023-12-11 15:59 ` Julien Grall
2023-12-11 16:05 ` Julien Grall
2023-12-11 17:36 ` Nicola Vetrini
2023-12-12 1:36 ` Stefano Stabellini
2023-12-12 9:23 ` Julien Grall
2023-12-12 15:49 ` Julien Grall
2023-12-13 14:02 ` Nicola Vetrini
2023-12-14 9:42 ` Julien Grall
2023-12-14 22:32 ` Stefano Stabellini
2023-12-15 11:03 ` Nicola Vetrini
2023-12-15 14:08 ` Nicola Vetrini
2023-12-15 18:18 ` Julien Grall
2023-12-15 21:02 ` Stefano Stabellini
2023-12-11 10:30 ` [XEN PATCH 6/7] x86/platform: removed break to address MISRA C:2012 Rule 2.1 Nicola Vetrini
2023-12-12 1:44 ` Stefano Stabellini
2023-12-12 10:13 ` Jan Beulich
2023-12-12 22:38 ` Stefano Stabellini
2023-12-13 10:43 ` Nicola Vetrini
2023-12-11 10:30 ` [XEN PATCH 7/7] x86/xstate: move BUILD_BUG_ON " Nicola Vetrini
2023-12-12 1:46 ` Stefano Stabellini
2023-12-12 10:04 ` Jan Beulich
2023-12-12 10:07 ` Jan Beulich
2023-12-12 13:38 ` Nicola Vetrini
2023-12-12 14:01 ` Jan Beulich
2023-12-12 14:05 ` Nicola Vetrini
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