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From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <kvmarm@lists.cs.columbia.edu>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<linux-pci@vger.kernel.org>
Cc: Marc Zyngier <maz@kernel.org>,
	Alex Williamson <alex.williamson@redhat.com>,
	Cornelia Huck <cohuck@redhat.com>,
	Nianyao Tang <tangnianyao@huawei.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Subject: Question on guest enable msi fail when using GICv4/4.1
Date: Fri, 7 May 2021 13:57:04 +0800	[thread overview]
Message-ID: <3a2c66d6-6ca0-8478-d24b-61e8e3241b20@hisilicon.com> (raw)

[This letter comes from Nianyao Tang]

Hi,

Using GICv4/4.1 and msi capability, guest vf driver requires 3 vectors and enable msi, will lead to
guest stuck. Qemu gets number of interrupts from Multiple Message Capable field set by guest. This
field is aligned to a power of 2(if a function requires 3 vectors, it initializes it to 2).
However, guest driver just sends 3 mapi-cmd to vits and 3 ite entries is recorded in host.
Vfio initializes msi interrupts using the number of interrupts 4 provide by qemu.
When it comes to the 4th msi without ite in vits, in irq_bypass_register_producer, producer
and consumer will __connect fail, due to find_ite fail, and do not resume guest.

Do we support this case, Guest function using msi interrupts number not aligned to a power of 2?
Or qemu should provide correct msi interrupts number?

Thanks,
Shaokun

WARNING: multiple messages have this Message-ID (diff)
From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <kvmarm@lists.cs.columbia.edu>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<linux-pci@vger.kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Marc Zyngier <maz@kernel.org>,
	Alex Williamson <alex.williamson@redhat.com>,
	Cornelia Huck <cohuck@redhat.com>
Subject: Question on guest enable msi fail when using GICv4/4.1
Date: Fri, 7 May 2021 13:57:04 +0800	[thread overview]
Message-ID: <3a2c66d6-6ca0-8478-d24b-61e8e3241b20@hisilicon.com> (raw)

[This letter comes from Nianyao Tang]

Hi,

Using GICv4/4.1 and msi capability, guest vf driver requires 3 vectors and enable msi, will lead to
guest stuck. Qemu gets number of interrupts from Multiple Message Capable field set by guest. This
field is aligned to a power of 2(if a function requires 3 vectors, it initializes it to 2).
However, guest driver just sends 3 mapi-cmd to vits and 3 ite entries is recorded in host.
Vfio initializes msi interrupts using the number of interrupts 4 provide by qemu.
When it comes to the 4th msi without ite in vits, in irq_bypass_register_producer, producer
and consumer will __connect fail, due to find_ite fail, and do not resume guest.

Do we support this case, Guest function using msi interrupts number not aligned to a power of 2?
Or qemu should provide correct msi interrupts number?

Thanks,
Shaokun
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <kvmarm@lists.cs.columbia.edu>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<linux-pci@vger.kernel.org>
Cc: Marc Zyngier <maz@kernel.org>,
	Alex Williamson <alex.williamson@redhat.com>,
	Cornelia Huck <cohuck@redhat.com>,
	Nianyao Tang <tangnianyao@huawei.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Subject: Question on guest enable msi fail when using GICv4/4.1
Date: Fri, 7 May 2021 13:57:04 +0800	[thread overview]
Message-ID: <3a2c66d6-6ca0-8478-d24b-61e8e3241b20@hisilicon.com> (raw)

[This letter comes from Nianyao Tang]

Hi,

Using GICv4/4.1 and msi capability, guest vf driver requires 3 vectors and enable msi, will lead to
guest stuck. Qemu gets number of interrupts from Multiple Message Capable field set by guest. This
field is aligned to a power of 2(if a function requires 3 vectors, it initializes it to 2).
However, guest driver just sends 3 mapi-cmd to vits and 3 ite entries is recorded in host.
Vfio initializes msi interrupts using the number of interrupts 4 provide by qemu.
When it comes to the 4th msi without ite in vits, in irq_bypass_register_producer, producer
and consumer will __connect fail, due to find_ite fail, and do not resume guest.

Do we support this case, Guest function using msi interrupts number not aligned to a power of 2?
Or qemu should provide correct msi interrupts number?

Thanks,
Shaokun

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

             reply	other threads:[~2021-05-07  5:57 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-07  5:57 Shaokun Zhang [this message]
2021-05-07  5:57 ` Question on guest enable msi fail when using GICv4/4.1 Shaokun Zhang
2021-05-07  5:57 ` Shaokun Zhang
2021-05-07  9:03 ` Marc Zyngier
2021-05-07  9:03   ` Marc Zyngier
2021-05-07  9:03   ` Marc Zyngier
2021-05-07  9:58   ` Shaokun Zhang
2021-05-07  9:58     ` Shaokun Zhang
2021-05-07  9:58     ` Shaokun Zhang
2021-05-07 11:02     ` Marc Zyngier
2021-05-07 11:02       ` Marc Zyngier
2021-05-07 11:02       ` Marc Zyngier
2021-05-07 17:36       ` Marc Zyngier
2021-05-07 17:36         ` Marc Zyngier
2021-05-08  1:51         ` Jason Wang
2021-05-08  1:51           ` Jason Wang
2021-05-08  1:51           ` Jason Wang
2021-05-08  6:56           ` Zhu, Lingshan
2021-05-08  6:56             ` Zhu, Lingshan
2021-05-08  6:56             ` Zhu, Lingshan
2021-05-08  9:15           ` Marc Zyngier
2021-05-08  9:15             ` Marc Zyngier
2021-05-08  9:15             ` Marc Zyngier
2021-05-09 17:00       ` Auger Eric
2021-05-09 17:00         ` Auger Eric
2021-05-09 17:00         ` Auger Eric
2021-05-10  7:49         ` Marc Zyngier
2021-05-10  7:49           ` Marc Zyngier
2021-05-10  7:49           ` Marc Zyngier
2021-05-10  8:29           ` Auger Eric
2021-05-10  8:29             ` Auger Eric
2021-05-10  8:29             ` Auger Eric
2021-05-10  9:59             ` Marc Zyngier
2021-05-10  9:59               ` Marc Zyngier
2021-05-10  9:59               ` Marc Zyngier

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