From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Shawn Guo" <shawnguo@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Mark Rutland" <mark.rutland@arm.com>, "Michael Turquette" <mturquette@baylibre.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Saravana Kannan" <saravanak@google.com>, "Angus Ainslie" <angus@akkea.ca>, "Martin Kepplinger" <martink@posteo.de>, "Matthias Kaehlcke" <mka@chromium.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Alexandre Bailon" <abailon@baylibre.com>, "Georgi Djakov" <georgi.djakov@linaro.org>, "Dong Aisheng" <aisheng.dong@nxp.com>, "Abel Vesa" <abel.vesa@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Fabio Estevam" <fabio.estevam@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/6] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Date: Thu, 31 Oct 2019 23:50:23 +0200 [thread overview] Message-ID: <3dd51e03a73f53f6cc7ec90c306d6cdbfa2204f7.1572558427.git.leonard.crestez@nxp.com> (raw) In-Reply-To: <cover.1572558427.git.leonard.crestez@nxp.com> In-Reply-To: <cover.1572558427.git.leonard.crestez@nxp.com> DRAM frequency switches are executed in firmware and can change the configuration of the DRAM PLL outside linux. Mark these CLKs with CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and recalculate rates. In current DRAM frequency tables on 8mm/8mn only the maximum frequency uses the PLL so it's always configured in the same way. However reading back the PLL configuration is the correct behavior and allows additional setpoints in the future. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> --- drivers/clk/imx/clk-imx8mm.c | 2 +- drivers/clk/imx/clk-imx8mn.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 7 +++++++ drivers/clk/imx/clk.h | 1 + 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index c58f988191a5..d500bac3afa1 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -326,11 +326,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) clks[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); - clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll); + clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); clks[IMX8MM_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000); clks[IMX8MM_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ca78cb1249a7..9c605ca1b631 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -323,11 +323,11 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); - clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll); + clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); clks[IMX8MN_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000); clks[IMX8MN_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000); diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 5c458199060a..a6d31a7262ef 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -65,10 +65,17 @@ struct imx_pll14xx_clk imx_1443x_pll = { .type = PLL_1443X, .rate_table = imx_pll1443x_tbl, .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), }; +struct imx_pll14xx_clk imx_1443x_dram_pll = { + .type = PLL_1443X, + .rate_table = imx_pll1443x_tbl, + .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), + .flags = CLK_GET_RATE_NOCACHE, +}; + struct imx_pll14xx_clk imx_1416x_pll = { .type = PLL_1416X, .rate_table = imx_pll1416x_tbl, .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), }; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index bc5bb6ac8636..81122c9ab842 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -50,10 +50,11 @@ struct imx_pll14xx_clk { int flags; }; extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; +extern struct imx_pll14xx_clk imx_1443x_dram_pll; #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Mark Rutland" <mark.rutland@arm.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Jacky Bai" <ping.bai@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "Michael Turquette" <mturquette@baylibre.com>, "Angus Ainslie" <angus@akkea.ca>, "Alexandre Bailon" <abailon@baylibre.com>, linux-clk@vger.kernel.org, "Abel Vesa" <abel.vesa@nxp.com>, "Saravana Kannan" <saravanak@google.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Matthias Kaehlcke" <mka@chromium.org>, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, "Martin Kepplinger" <martink@posteo.de>, linux-arm-kernel@lists.infradead.org, "Dong Aisheng" <aisheng.dong@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, kernel@pengutronix.de, "Fabio Estevam" <fabio.estevam@nxp.com>, "Shawn Guo" <shawnguo@kernel.org>, "Georgi Djakov" <georgi.djakov@linaro.org> Subject: [PATCH v3 2/6] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Date: Thu, 31 Oct 2019 23:50:23 +0200 [thread overview] Message-ID: <3dd51e03a73f53f6cc7ec90c306d6cdbfa2204f7.1572558427.git.leonard.crestez@nxp.com> (raw) In-Reply-To: <cover.1572558427.git.leonard.crestez@nxp.com> In-Reply-To: <cover.1572558427.git.leonard.crestez@nxp.com> DRAM frequency switches are executed in firmware and can change the configuration of the DRAM PLL outside linux. Mark these CLKs with CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and recalculate rates. In current DRAM frequency tables on 8mm/8mn only the maximum frequency uses the PLL so it's always configured in the same way. However reading back the PLL configuration is the correct behavior and allows additional setpoints in the future. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> --- drivers/clk/imx/clk-imx8mm.c | 2 +- drivers/clk/imx/clk-imx8mn.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 7 +++++++ drivers/clk/imx/clk.h | 1 + 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index c58f988191a5..d500bac3afa1 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -326,11 +326,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) clks[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); - clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll); + clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); clks[IMX8MM_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000); clks[IMX8MM_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ca78cb1249a7..9c605ca1b631 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -323,11 +323,11 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); - clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll); + clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); clks[IMX8MN_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000); clks[IMX8MN_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000); diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 5c458199060a..a6d31a7262ef 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -65,10 +65,17 @@ struct imx_pll14xx_clk imx_1443x_pll = { .type = PLL_1443X, .rate_table = imx_pll1443x_tbl, .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), }; +struct imx_pll14xx_clk imx_1443x_dram_pll = { + .type = PLL_1443X, + .rate_table = imx_pll1443x_tbl, + .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), + .flags = CLK_GET_RATE_NOCACHE, +}; + struct imx_pll14xx_clk imx_1416x_pll = { .type = PLL_1416X, .rate_table = imx_pll1416x_tbl, .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), }; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index bc5bb6ac8636..81122c9ab842 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -50,10 +50,11 @@ struct imx_pll14xx_clk { int flags; }; extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; +extern struct imx_pll14xx_clk imx_1443x_dram_pll; #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-10-31 21:50 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-31 21:50 [PATCH v3 0/6] PM / devfreq: Add dynamic scaling for imx ddr controller Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez 2019-10-31 21:50 ` [PATCH v3 1/6] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez 2019-12-02 3:12 ` Shawn Guo 2019-12-02 3:12 ` Shawn Guo 2019-12-02 4:19 ` Leonard Crestez 2019-12-02 4:19 ` Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez [this message] 2019-10-31 21:50 ` [PATCH v3 2/6] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez 2019-10-31 21:50 ` [PATCH v3 3/6] dt-bindings: devfreq: Add bindings for imx ddr controller Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez 2019-11-04 22:21 ` Rob Herring 2019-11-04 22:21 ` Rob Herring 2019-11-05 19:25 ` Leonard Crestez 2019-11-05 19:25 ` Leonard Crestez 2019-11-05 20:13 ` Rob Herring 2019-11-05 20:13 ` Rob Herring 2019-10-31 21:50 ` [PATCH v3 4/6] PM / devfreq: Add dynamic scaling " Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez 2019-12-02 5:38 ` Shawn Guo 2019-12-02 5:38 ` Shawn Guo 2019-12-02 9:12 ` Leonard Crestez 2019-12-02 9:12 ` Leonard Crestez 2019-12-02 13:34 ` Shawn Guo 2019-12-02 13:34 ` Shawn Guo 2019-10-31 21:50 ` [PATCH v3 5/6] PM / devfreq: imx-ddrc: Measure bandwidth with perf Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez 2019-10-31 21:50 ` [PATCH v3 6/6] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez 2019-10-31 21:50 ` Leonard Crestez 2019-11-04 22:01 ` Rob Herring 2019-11-04 22:01 ` Rob Herring 2019-11-11 14:29 ` Leonard Crestez 2019-11-11 14:29 ` Leonard Crestez
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=3dd51e03a73f53f6cc7ec90c306d6cdbfa2204f7.1572558427.git.leonard.crestez@nxp.com \ --to=leonard.crestez@nxp.com \ --cc=Anson.Huang@nxp.com \ --cc=a.swigon@partner.samsung.com \ --cc=abailon@baylibre.com \ --cc=abel.vesa@nxp.com \ --cc=aisheng.dong@nxp.com \ --cc=angus@akkea.ca \ --cc=cw00.choi@samsung.com \ --cc=devicetree@vger.kernel.org \ --cc=fabio.estevam@nxp.com \ --cc=georgi.djakov@linaro.org \ --cc=kernel@pengutronix.de \ --cc=krzk@kernel.org \ --cc=kyungmin.park@samsung.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-imx@nxp.com \ --cc=linux-pm@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=martink@posteo.de \ --cc=mka@chromium.org \ --cc=mturquette@baylibre.com \ --cc=myungjoo.ham@samsung.com \ --cc=ping.bai@nxp.com \ --cc=rjw@rjwysocki.net \ --cc=robh+dt@kernel.org \ --cc=saravanak@google.com \ --cc=sboyd@kernel.org \ --cc=shawnguo@kernel.org \ --cc=viresh.kumar@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.