From: Stafford Horne <shorne@gmail.com> To: QEMU Development <qemu-devel@nongnu.org> Cc: Openrisc <openrisc@lists.librecores.org>, "Tim \\'mithro\\' Ansell" <mithro@mithis.com>, Stafford Horne <shorne@gmail.com> Subject: [Qemu-devel] [PATCH v2 2/9] target/openrisc: Implement EPH bit Date: Mon, 24 Apr 2017 07:40:50 +0900 [thread overview] Message-ID: <3fee028d1ea02cd16470dc5c65d54974ef85b673.1492986468.git.shorne@gmail.com> (raw) In-Reply-To: <cover.1492986468.git.shorne@gmail.com> In-Reply-To: <cover.1492986468.git.shorne@gmail.com> From: Tim 'mithro' Ansell <mithro@mithis.com> Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9..2c91fab 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |= env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |= 0xf0000000; + } env->pc = vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); -- 2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com> To: openrisc@lists.librecores.org Subject: [OpenRISC] [PATCH v2 2/9] target/openrisc: Implement EPH bit Date: Mon, 24 Apr 2017 07:40:50 +0900 [thread overview] Message-ID: <3fee028d1ea02cd16470dc5c65d54974ef85b673.1492986468.git.shorne@gmail.com> (raw) In-Reply-To: <cover.1492986468.git.shorne@gmail.com> From: Tim 'mithro' Ansell <mithro@mithis.com> Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9..2c91fab 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |= env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |= 0xf0000000; + } env->pc = vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); -- 2.9.3
next prev parent reply other threads:[~2017-04-23 22:41 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-23 22:40 [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 1/9] target/openrisc: Implement EVBAR register Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` Stafford Horne [this message] 2017-04-23 22:40 ` [OpenRISC] [PATCH v2 2/9] target/openrisc: Implement EPH bit Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 3/9] target/openrisc: Fixes for memory debugging Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 4/9] target/openrisc: add numcores and coreid support Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 5/9] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 6/9] target/openrisc: implement shadow registers Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 7/9] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 8/9] target/openrisc: Implement full vmstate serialization Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 9/9] target/openrisc: Remove duplicate features property Stafford Horne 2017-04-23 22:40 ` [OpenRISC] " Stafford Horne 2017-04-24 0:09 ` [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes no-reply 2017-04-24 0:09 ` [OpenRISC] " no-reply
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