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From: Baruch Siach <baruch@tkos.co.il>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <bgolaszewski@baylibre.com>
Cc: Baruch Siach <baruch@tkos.co.il>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Ralph Sennhauser <ralph.sennhauser@gmail.com>,
	linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] gpio: mvebu: update Armada XP per-CPU comment
Date: Wed, 18 Nov 2020 12:30:42 +0200	[thread overview]
Message-ID: <42dec69070e1f2b09b29606247635a57f780b765.1605694661.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1605694661.git.baruch@tkos.co.il>

Commit 2233bf7a92e ("gpio: mvebu: switch to regmap for register access")
introduced percpu_regs to replace percpu_membase. Update the comment to
match.

Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Fixes: 2233bf7a92e7 ("gpio: mvebu: switch to regmap for register access")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 drivers/gpio/gpio-mvebu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 433e2c3f3fd5..bdc4d813a42e 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -78,8 +78,7 @@
 
 /*
  * The Armada XP has per-CPU registers for interrupt cause, interrupt
- * mask and interrupt level mask. Those are relative to the
- * percpu_membase.
+ * mask and interrupt level mask. Those are in percpu_regs range.
  */
 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
-- 
2.29.2


WARNING: multiple messages have this Message-ID (diff)
From: Baruch Siach <baruch@tkos.co.il>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <bgolaszewski@baylibre.com>
Cc: Andrew Lunn <andrew@lunn.ch>, Baruch Siach <baruch@tkos.co.il>,
	Jason Cooper <jason@lakedaemon.net>,
	linux-pwm@vger.kernel.org,
	Gregory Clement <gregory.clement@bootlin.com>,
	linux-gpio@vger.kernel.org,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Ralph Sennhauser <ralph.sennhauser@gmail.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	linux-arm-kernel@lists.infradead.org,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: [PATCH 1/5] gpio: mvebu: update Armada XP per-CPU comment
Date: Wed, 18 Nov 2020 12:30:42 +0200	[thread overview]
Message-ID: <42dec69070e1f2b09b29606247635a57f780b765.1605694661.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1605694661.git.baruch@tkos.co.il>

Commit 2233bf7a92e ("gpio: mvebu: switch to regmap for register access")
introduced percpu_regs to replace percpu_membase. Update the comment to
match.

Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Fixes: 2233bf7a92e7 ("gpio: mvebu: switch to regmap for register access")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 drivers/gpio/gpio-mvebu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 433e2c3f3fd5..bdc4d813a42e 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -78,8 +78,7 @@
 
 /*
  * The Armada XP has per-CPU registers for interrupt cause, interrupt
- * mask and interrupt level mask. Those are relative to the
- * percpu_membase.
+ * mask and interrupt level mask. Those are in percpu_regs range.
  */
 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
-- 
2.29.2


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  reply	other threads:[~2020-11-18 10:47 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-18 10:30 [PATCH 0/5] gpio: mvebu: Armada 8K/7K PWM support Baruch Siach
2020-11-18 10:30 ` Baruch Siach
2020-11-18 10:30 ` Baruch Siach [this message]
2020-11-18 10:30   ` [PATCH 1/5] gpio: mvebu: update Armada XP per-CPU comment Baruch Siach
2020-11-18 22:47   ` Andrew Lunn
2020-11-18 22:47     ` Andrew Lunn
2020-11-18 10:30 ` [PATCH 2/5] gpio: mvebu: switch pwm duration registers to regmap Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 22:59   ` Andrew Lunn
2020-11-18 22:59     ` Andrew Lunn
2020-11-18 10:30 ` [PATCH 3/5] gpio: mvebu: add pwm support for Armada 8K/7K Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 23:18   ` Andrew Lunn
2020-11-18 23:18     ` Andrew Lunn
2020-11-19  6:21     ` Baruch Siach
2020-11-19  6:21       ` Baruch Siach
2020-11-19 13:34       ` Andrew Lunn
2020-11-19 13:34         ` Andrew Lunn
2020-11-19 13:47         ` Baruch Siach
2020-11-19 13:47           ` Baruch Siach
2020-12-01 18:16           ` Bartosz Golaszewski
2020-12-01 18:16             ` Bartosz Golaszewski
2020-12-01 18:21             ` Baruch Siach
2020-12-01 18:21               ` Baruch Siach
2020-11-18 10:30 ` [PATCH 4/5] arm64: dts: armada: add pwm offsets for ap/cp gpios Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 10:30 ` [PATCH 5/5] dt-bindings: ap806: document gpio pwm-offset property Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 22:46 ` [PATCH 0/5] gpio: mvebu: Armada 8K/7K PWM support Andrew Lunn
2020-11-18 22:46   ` Andrew Lunn
2020-11-19  5:49   ` Baruch Siach
2020-11-19  5:49     ` Baruch Siach

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