From: Jingyi Wang <wangjingyi11@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>,
<maz@kernel.org>
Cc: chengjian8@huawei.com, Martin.Weidmann@arm.com
Subject: Report an error on GICv4.1 vcpu de-schedule
Date: Thu, 17 Mar 2022 15:27:45 +0800 [thread overview]
Message-ID: <4aae10ba-b39a-5f84-754b-69c2eb0a2c03@huawei.com> (raw)
Hi Marc，
The patch "KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty
bit"(57e3cebd022fbc035dcf190ac789fd2ffc747f5b) remove the polling of
GICR_VPENDBASER.Dirty bit in vcpu_load() , while check the VPT parsing
ready in kvm_vgic_flush_hwstate() for better performance.
Most time it works, but we have met an error on our hardware recently.
In preemptable kernel, the vcpu can be preempted between vcpu_load and
kvm_vgic_flush_hwstate. As a result, it get de-scheduled and
its_clear_vpend_valid() is called
val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
val &= ~GICR_VPENDBASER_Valid;
val &= ~clr;
val |= set;
gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
The function clears Valid bit meanwhile GICR_VPENDBASER_Dirty
maybe still 1, which cause the subsequent GICR_VPENDBASER_Dirty polling
fail and report ""ITS virtual pending table not cleaning".
We have communicated with Martin from ARM and get the conclusion
that we should not change valid bit while the dirty bit not clear——
"The dirty bit reports whether the last schedule /de-schedule
operation has completed.The restriction on not changing Valid when Dirty
is 1, is so that hardware can always complete the last operation for
starting the next".
I think maybe we can check dirty bit clear before clearing the valid bit
in its_clear_vpend_valid() code. Hope to know your opinion about this
issue.
Thanks,
Jingyi
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Jingyi Wang <wangjingyi11@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>,
<maz@kernel.org>
Cc: "wanghaibin.wang@huawei.com" <wanghaibin.wang@huawei.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
<Martin.Weidmann@arm.com>, <tangnianyao@huawei.com>,
<chengjian8@huawei.com>, Jingyi Wang <wangjingyi11@huawei.com>
Subject: Report an error on GICv4.1 vcpu de-schedule
Date: Thu, 17 Mar 2022 15:27:45 +0800 [thread overview]
Message-ID: <4aae10ba-b39a-5f84-754b-69c2eb0a2c03@huawei.com> (raw)
Hi Marc，
The patch "KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty
bit"(57e3cebd022fbc035dcf190ac789fd2ffc747f5b) remove the polling of
GICR_VPENDBASER.Dirty bit in vcpu_load() , while check the VPT parsing
ready in kvm_vgic_flush_hwstate() for better performance.
Most time it works, but we have met an error on our hardware recently.
In preemptable kernel, the vcpu can be preempted between vcpu_load and
kvm_vgic_flush_hwstate. As a result, it get de-scheduled and
its_clear_vpend_valid() is called
val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
val &= ~GICR_VPENDBASER_Valid;
val &= ~clr;
val |= set;
gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
The function clears Valid bit meanwhile GICR_VPENDBASER_Dirty
maybe still 1, which cause the subsequent GICR_VPENDBASER_Dirty polling
fail and report ""ITS virtual pending table not cleaning".
We have communicated with Martin from ARM and get the conclusion
that we should not change valid bit while the dirty bit not clear——
"The dirty bit reports whether the last schedule /de-schedule
operation has completed.The restriction on not changing Valid when Dirty
is 1, is so that hardware can always complete the last operation for
starting the next".
I think maybe we can check dirty bit clear before clearing the valid bit
in its_clear_vpend_valid() code. Hope to know your opinion about this
issue.
Thanks,
Jingyi
WARNING: multiple messages have this Message-ID (diff)
From: Jingyi Wang <wangjingyi11@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>,
<maz@kernel.org>
Cc: "wanghaibin.wang@huawei.com" <wanghaibin.wang@huawei.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
<Martin.Weidmann@arm.com>, <tangnianyao@huawei.com>,
<chengjian8@huawei.com>, Jingyi Wang <wangjingyi11@huawei.com>
Subject: Report an error on GICv4.1 vcpu de-schedule
Date: Thu, 17 Mar 2022 15:27:45 +0800 [thread overview]
Message-ID: <4aae10ba-b39a-5f84-754b-69c2eb0a2c03@huawei.com> (raw)
Hi Marc，
The patch "KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty
bit"(57e3cebd022fbc035dcf190ac789fd2ffc747f5b) remove the polling of
GICR_VPENDBASER.Dirty bit in vcpu_load() , while check the VPT parsing
ready in kvm_vgic_flush_hwstate() for better performance.
Most time it works, but we have met an error on our hardware recently.
In preemptable kernel, the vcpu can be preempted between vcpu_load and
kvm_vgic_flush_hwstate. As a result, it get de-scheduled and
its_clear_vpend_valid() is called
val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
val &= ~GICR_VPENDBASER_Valid;
val &= ~clr;
val |= set;
gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
The function clears Valid bit meanwhile GICR_VPENDBASER_Dirty
maybe still 1, which cause the subsequent GICR_VPENDBASER_Dirty polling
fail and report ""ITS virtual pending table not cleaning".
We have communicated with Martin from ARM and get the conclusion
that we should not change valid bit while the dirty bit not clear——
"The dirty bit reports whether the last schedule /de-schedule
operation has completed.The restriction on not changing Valid when Dirty
is 1, is so that hardware can always complete the last operation for
starting the next".
I think maybe we can check dirty bit clear before clearing the valid bit
in its_clear_vpend_valid() code. Hope to know your opinion about this
issue.
Thanks,
Jingyi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2022-03-17 7:28 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-17 7:27 Jingyi Wang [this message]
2022-03-17 7:27 ` Report an error on GICv4.1 vcpu de-schedule Jingyi Wang
2022-03-17 7:27 ` Jingyi Wang
2022-03-17 10:17 ` Marc Zyngier
2022-03-17 10:17 ` Marc Zyngier
2022-03-17 10:17 ` Marc Zyngier
2022-03-18 6:14 ` Jingyi Wang
2022-03-18 6:14 ` Jingyi Wang
2022-03-18 6:14 ` Jingyi Wang
2022-03-21 1:33 ` Jingyi Wang
2022-03-21 1:33 ` Jingyi Wang
2022-03-21 1:33 ` Jingyi Wang
2022-03-21 8:59 ` [irqchip: irq/irqchip-next] irqchip/gic-v4: Wait for GICR_VPENDBASER.Dirty to clear before descheduling irqchip-bot for Marc Zyngier
2022-03-21 14:07 ` irqchip-bot for Marc Zyngier
2022-04-05 15:40 ` [irqchip: irq/irqchip-fixes] " irqchip-bot for Marc Zyngier
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