From: Joshua Clayton <stillcompiling@gmail.com>
To: Alan Tull <atull@opensource.altera.com>,
Moritz Fischer <moritz.fischer@ettus.com>,
Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <fabio.estevam@nxp.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Anatolij Gustschin <agust@denx.de>,
Joshua Clayton <stillcompiling@gmail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-fpga@vger.kernel.org
Subject: [PATCH v6 3/5] doc: dt: add cyclone-ps-spi binding document
Date: Fri, 16 Dec 2016 15:17:52 -0800 [thread overview]
Message-ID: <526ee1b336cf2ab9473041762cf55018b6156dd4.1481918884.git.stillcompiling@gmail.com> (raw)
In-Reply-To: <cover.1481918884.git.stillcompiling@gmail.com>
In-Reply-To: <cover.1481918884.git.stillcompiling@gmail.com>
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
new file mode 100644
index 0000000..3f515c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
@@ -0,0 +1,25 @@
+Altera Cyclone Passive Serial SPI FPGA Manager
+
+Altera Cyclone FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically spi, and might require extra
+circuits in order to play nicely with other spi slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible : should contain "altr,cyclone-ps-spi-fpga-mgr"
+- reg : spi slave id of the fpga
+- config-gpios : config pin (referred to as nCONFIG in the cyclone manual)
+- status-gpios : status pin (referred to as nSTATUS in the cyclone manual)
+
+both gpios pins are normally active low open drain.
+
+Example:
+ fpga_spi: evi-fpga-spi@0 {
+ compatible = "altr,cyclone-ps-spi-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ config-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ };
--
2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: Joshua Clayton <stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Alan Tull
<atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
Moritz Fischer
<moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>,
Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>,
Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org>,
Joshua Clayton
<stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v6 3/5] doc: dt: add cyclone-ps-spi binding document
Date: Fri, 16 Dec 2016 15:17:52 -0800 [thread overview]
Message-ID: <526ee1b336cf2ab9473041762cf55018b6156dd4.1481918884.git.stillcompiling@gmail.com> (raw)
In-Reply-To: <cover.1481918884.git.stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
In-Reply-To: <cover.1481918884.git.stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton <stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
new file mode 100644
index 0000000..3f515c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
@@ -0,0 +1,25 @@
+Altera Cyclone Passive Serial SPI FPGA Manager
+
+Altera Cyclone FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically spi, and might require extra
+circuits in order to play nicely with other spi slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible : should contain "altr,cyclone-ps-spi-fpga-mgr"
+- reg : spi slave id of the fpga
+- config-gpios : config pin (referred to as nCONFIG in the cyclone manual)
+- status-gpios : status pin (referred to as nSTATUS in the cyclone manual)
+
+both gpios pins are normally active low open drain.
+
+Example:
+ fpga_spi: evi-fpga-spi@0 {
+ compatible = "altr,cyclone-ps-spi-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ config-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ };
--
2.9.3
--
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WARNING: multiple messages have this Message-ID (diff)
From: stillcompiling@gmail.com (Joshua Clayton)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 3/5] doc: dt: add cyclone-ps-spi binding document
Date: Fri, 16 Dec 2016 15:17:52 -0800 [thread overview]
Message-ID: <526ee1b336cf2ab9473041762cf55018b6156dd4.1481918884.git.stillcompiling@gmail.com> (raw)
In-Reply-To: <cover.1481918884.git.stillcompiling@gmail.com>
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
new file mode 100644
index 0000000..3f515c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
@@ -0,0 +1,25 @@
+Altera Cyclone Passive Serial SPI FPGA Manager
+
+Altera Cyclone FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically spi, and might require extra
+circuits in order to play nicely with other spi slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible : should contain "altr,cyclone-ps-spi-fpga-mgr"
+- reg : spi slave id of the fpga
+- config-gpios : config pin (referred to as nCONFIG in the cyclone manual)
+- status-gpios : status pin (referred to as nSTATUS in the cyclone manual)
+
+both gpios pins are normally active low open drain.
+
+Example:
+ fpga_spi: evi-fpga-spi at 0 {
+ compatible = "altr,cyclone-ps-spi-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ config-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ };
--
2.9.3
next prev parent reply other threads:[~2016-12-16 23:18 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-16 23:17 [PATCH v6 0/5] Altera Cyclone Passive Serial SPI FPGA Manager Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` [PATCH v6 1/5] lib: add bitrev8x4() Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` [PATCH v6 2/5] lib: implement __arch_bitrev8x4() Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-19 10:06 ` Will Deacon
2016-12-19 10:06 ` Will Deacon
2016-12-20 17:22 ` Joshua Clayton
2016-12-20 17:22 ` Joshua Clayton
2016-12-20 17:22 ` Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton [this message]
2016-12-16 23:17 ` [PATCH v6 3/5] doc: dt: add cyclone-ps-spi binding document Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-19 2:19 ` Alan Tull
2016-12-19 2:19 ` Alan Tull
2016-12-19 2:19 ` Alan Tull
2016-12-16 23:17 ` [PATCH v6 4/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-19 7:23 ` Uwe Kleine-König
2016-12-19 7:23 ` Uwe Kleine-König
2016-12-20 19:47 ` Joshua Clayton
2016-12-20 19:47 ` Joshua Clayton
2016-12-20 19:47 ` Joshua Clayton
2016-12-20 20:44 ` Uwe Kleine-König
2016-12-20 20:44 ` Uwe Kleine-König
2016-12-16 23:17 ` [PATCH v6 5/5] ARM: dts: imx6q-evi: support cyclone-ps-spi Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-16 23:17 ` Joshua Clayton
2016-12-19 2:23 ` Alan Tull
2016-12-19 2:23 ` Alan Tull
2016-12-19 2:23 ` Alan Tull
2016-12-19 2:14 ` [PATCH v6 0/5] Altera Cyclone Passive Serial SPI FPGA Manager Alan Tull
2016-12-19 2:14 ` Alan Tull
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