From: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> To: Linux Doc Mailing List <linux-doc@vger.kernel.org> Cc: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>, Mauro Carvalho Chehab <mchehab@infradead.org>, linux-kernel@vger.kernel.org, Jonathan Corbet <corbet@lwn.net>, Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org Subject: [PATCH v3 24/33] docs: riscv: convert docs to ReST and rename to *.rst Date: Sat, 8 Jun 2019 23:27:14 -0300 [thread overview] Message-ID: <55623342910f7ef470a3c49a3d42cfb23fb12e76.1560045490.git.mchehab+samsung@kernel.org> (raw) In-Reply-To: <cover.1560045490.git.mchehab+samsung@kernel.org> The conversion here is trivial: - Adjust the document title's markup - Do some whitespace alignment; - mark literal blocks; - Use ReST way to markup indented lists. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> --- Documentation/riscv/index.rst | 17 ++++ Documentation/riscv/{pmu.txt => pmu.rst} | 98 +++++++++++++----------- 2 files changed, 69 insertions(+), 46 deletions(-) create mode 100644 Documentation/riscv/index.rst rename Documentation/riscv/{pmu.txt => pmu.rst} (77%) diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst new file mode 100644 index 000000000000..c4b906d9b5a7 --- /dev/null +++ b/Documentation/riscv/index.rst @@ -0,0 +1,17 @@ +:orphan: + +=================== +RISC-V architecture +=================== + +.. toctree:: + :maxdepth: 1 + + pmu + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.rst similarity index 77% rename from Documentation/riscv/pmu.txt rename to Documentation/riscv/pmu.rst index b29f03a6d82f..acb216b99c26 100644 --- a/Documentation/riscv/pmu.txt +++ b/Documentation/riscv/pmu.rst @@ -1,5 +1,7 @@ +=================================== Supporting PMUs on RISC-V platforms -========================================== +=================================== + Alan Kao <alankao@andestech.com>, Mar 2018 Introduction @@ -77,13 +79,13 @@ Note that some features can be done in this stage as well: (2) privilege level setting (user space only, kernel space only, both); (3) destructor setting. Normally it is sufficient to apply *riscv_destroy_event*; (4) tweaks for non-sampling events, which will be utilized by functions such as -*perf_adjust_period*, usually something like the follows: + *perf_adjust_period*, usually something like the follows:: -if (!is_sampling_event(event)) { - hwc->sample_period = x86_pmu.max_period; - hwc->last_period = hwc->sample_period; - local64_set(&hwc->period_left, hwc->sample_period); -} + if (!is_sampling_event(event)) { + hwc->sample_period = x86_pmu.max_period; + hwc->last_period = hwc->sample_period; + local64_set(&hwc->period_left, hwc->sample_period); + } In the case of *riscv_base_pmu*, only (3) is provided for now. @@ -94,10 +96,10 @@ In the case of *riscv_base_pmu*, only (3) is provided for now. 3.1. Interrupt Initialization This often occurs at the beginning of the *event_init* method. In common -practice, this should be a code segment like +practice, this should be a code segment like:: -int x86_reserve_hardware(void) -{ + int x86_reserve_hardware(void) + { int err = 0; if (!atomic_inc_not_zero(&pmc_refcount)) { @@ -114,7 +116,7 @@ int x86_reserve_hardware(void) } return err; -} + } And the magic is in *reserve_pmc_hardware*, which usually does atomic operations to make implemented IRQ accessible from some global function pointer. @@ -128,28 +130,28 @@ which will be introduced in the next section.) 3.2. IRQ Structure -Basically, a IRQ runs the following pseudo code: +Basically, a IRQ runs the following pseudo code:: -for each hardware counter that triggered this overflow + for each hardware counter that triggered this overflow - get the event of this counter + get the event of this counter - // following two steps are defined as *read()*, - // check the section Reading/Writing Counters for details. - count the delta value since previous interrupt - update the event->count (# event occurs) by adding delta, and - event->hw.period_left by subtracting delta + // following two steps are defined as *read()*, + // check the section Reading/Writing Counters for details. + count the delta value since previous interrupt + update the event->count (# event occurs) by adding delta, and + event->hw.period_left by subtracting delta - if the event overflows - sample data - set the counter appropriately for the next overflow + if the event overflows + sample data + set the counter appropriately for the next overflow - if the event overflows again - too frequently, throttle this event - fi - fi + if the event overflows again + too frequently, throttle this event + fi + fi -end for + end for However as of this writing, none of the RISC-V implementations have designed an interrupt for perf, so the details are to be completed in the future. @@ -195,23 +197,26 @@ A normal flow of these state transitions are as follows: At this stage, a general event is bound to a physical counter, if any. The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, because it is now stopped, and the (software) event count does not need updating. -** *start* is then called, and the counter is enabled. - With flag PERF_EF_RELOAD, it writes an appropriate value to the counter (check - previous section for detail). - Nothing is written if the flag does not contain PERF_EF_RELOAD. - The state now is reset to none, because it is neither stopped nor updated - (the counting already started) + + - *start* is then called, and the counter is enabled. + With flag PERF_EF_RELOAD, it writes an appropriate value to the counter (check + previous section for detail). + Nothing is written if the flag does not contain PERF_EF_RELOAD. + The state now is reset to none, because it is neither stopped nor updated + (the counting already started) + * When being context-switched out, *del* is called. It then checks out all the events in the PMU and calls *stop* to update their counts. -** *stop* is called by *del* - and the perf core with flag PERF_EF_UPDATE, and it often shares the same - subroutine as *read* with the same logic. - The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, again. -** Life cycle of these two pairs: *add* and *del* are called repeatedly as - tasks switch in-and-out; *start* and *stop* is also called when the perf core - needs a quick stop-and-start, for instance, when the interrupt period is being - adjusted. + - *stop* is called by *del* + and the perf core with flag PERF_EF_UPDATE, and it often shares the same + subroutine as *read* with the same logic. + The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, again. + + - Life cycle of these two pairs: *add* and *del* are called repeatedly as + tasks switch in-and-out; *start* and *stop* is also called when the perf core + needs a quick stop-and-start, for instance, when the interrupt period is being + adjusted. Current implementation is sufficient for now and can be easily extended to features in the future. @@ -225,25 +230,26 @@ A. Related Structures Both structures are designed to be read-only. *struct pmu* defines some function pointer interfaces, and most of them take -*struct perf_event* as a main argument, dealing with perf events according to -perf's internal state machine (check kernel/events/core.c for details). + *struct perf_event* as a main argument, dealing with perf events according to + perf's internal state machine (check kernel/events/core.c for details). *struct riscv_pmu* defines PMU-specific parameters. The naming follows the -convention of all other architectures. + convention of all other architectures. * struct perf_event: include/linux/perf_event.h * struct hw_perf_event The generic structure that represents perf events, and the hardware-related -details. + details. * struct riscv_hw_events: arch/riscv/include/asm/perf_event.h The structure that holds the status of events, has two fixed members: -the number of events and the array of the events. + the number of events and the array of the events. References ---------- [1] https://github.com/riscv/riscv-linux/pull/124 + [2] https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/f19TmCNP6yA -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> To: Linux Doc Mailing List <linux-doc@vger.kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Palmer Dabbelt <palmer@sifive.com>, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab <mchehab@infradead.org>, Mauro Carvalho Chehab <mchehab+samsung@kernel.org>, linux-riscv@lists.infradead.org Subject: [PATCH v3 24/33] docs: riscv: convert docs to ReST and rename to *.rst Date: Sat, 8 Jun 2019 23:27:14 -0300 [thread overview] Message-ID: <55623342910f7ef470a3c49a3d42cfb23fb12e76.1560045490.git.mchehab+samsung@kernel.org> (raw) In-Reply-To: <cover.1560045490.git.mchehab+samsung@kernel.org> The conversion here is trivial: - Adjust the document title's markup - Do some whitespace alignment; - mark literal blocks; - Use ReST way to markup indented lists. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> --- Documentation/riscv/index.rst | 17 ++++ Documentation/riscv/{pmu.txt => pmu.rst} | 98 +++++++++++++----------- 2 files changed, 69 insertions(+), 46 deletions(-) create mode 100644 Documentation/riscv/index.rst rename Documentation/riscv/{pmu.txt => pmu.rst} (77%) diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst new file mode 100644 index 000000000000..c4b906d9b5a7 --- /dev/null +++ b/Documentation/riscv/index.rst @@ -0,0 +1,17 @@ +:orphan: + +=================== +RISC-V architecture +=================== + +.. toctree:: + :maxdepth: 1 + + pmu + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.rst similarity index 77% rename from Documentation/riscv/pmu.txt rename to Documentation/riscv/pmu.rst index b29f03a6d82f..acb216b99c26 100644 --- a/Documentation/riscv/pmu.txt +++ b/Documentation/riscv/pmu.rst @@ -1,5 +1,7 @@ +=================================== Supporting PMUs on RISC-V platforms -========================================== +=================================== + Alan Kao <alankao@andestech.com>, Mar 2018 Introduction @@ -77,13 +79,13 @@ Note that some features can be done in this stage as well: (2) privilege level setting (user space only, kernel space only, both); (3) destructor setting. Normally it is sufficient to apply *riscv_destroy_event*; (4) tweaks for non-sampling events, which will be utilized by functions such as -*perf_adjust_period*, usually something like the follows: + *perf_adjust_period*, usually something like the follows:: -if (!is_sampling_event(event)) { - hwc->sample_period = x86_pmu.max_period; - hwc->last_period = hwc->sample_period; - local64_set(&hwc->period_left, hwc->sample_period); -} + if (!is_sampling_event(event)) { + hwc->sample_period = x86_pmu.max_period; + hwc->last_period = hwc->sample_period; + local64_set(&hwc->period_left, hwc->sample_period); + } In the case of *riscv_base_pmu*, only (3) is provided for now. @@ -94,10 +96,10 @@ In the case of *riscv_base_pmu*, only (3) is provided for now. 3.1. Interrupt Initialization This often occurs at the beginning of the *event_init* method. In common -practice, this should be a code segment like +practice, this should be a code segment like:: -int x86_reserve_hardware(void) -{ + int x86_reserve_hardware(void) + { int err = 0; if (!atomic_inc_not_zero(&pmc_refcount)) { @@ -114,7 +116,7 @@ int x86_reserve_hardware(void) } return err; -} + } And the magic is in *reserve_pmc_hardware*, which usually does atomic operations to make implemented IRQ accessible from some global function pointer. @@ -128,28 +130,28 @@ which will be introduced in the next section.) 3.2. IRQ Structure -Basically, a IRQ runs the following pseudo code: +Basically, a IRQ runs the following pseudo code:: -for each hardware counter that triggered this overflow + for each hardware counter that triggered this overflow - get the event of this counter + get the event of this counter - // following two steps are defined as *read()*, - // check the section Reading/Writing Counters for details. - count the delta value since previous interrupt - update the event->count (# event occurs) by adding delta, and - event->hw.period_left by subtracting delta + // following two steps are defined as *read()*, + // check the section Reading/Writing Counters for details. + count the delta value since previous interrupt + update the event->count (# event occurs) by adding delta, and + event->hw.period_left by subtracting delta - if the event overflows - sample data - set the counter appropriately for the next overflow + if the event overflows + sample data + set the counter appropriately for the next overflow - if the event overflows again - too frequently, throttle this event - fi - fi + if the event overflows again + too frequently, throttle this event + fi + fi -end for + end for However as of this writing, none of the RISC-V implementations have designed an interrupt for perf, so the details are to be completed in the future. @@ -195,23 +197,26 @@ A normal flow of these state transitions are as follows: At this stage, a general event is bound to a physical counter, if any. The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, because it is now stopped, and the (software) event count does not need updating. -** *start* is then called, and the counter is enabled. - With flag PERF_EF_RELOAD, it writes an appropriate value to the counter (check - previous section for detail). - Nothing is written if the flag does not contain PERF_EF_RELOAD. - The state now is reset to none, because it is neither stopped nor updated - (the counting already started) + + - *start* is then called, and the counter is enabled. + With flag PERF_EF_RELOAD, it writes an appropriate value to the counter (check + previous section for detail). + Nothing is written if the flag does not contain PERF_EF_RELOAD. + The state now is reset to none, because it is neither stopped nor updated + (the counting already started) + * When being context-switched out, *del* is called. It then checks out all the events in the PMU and calls *stop* to update their counts. -** *stop* is called by *del* - and the perf core with flag PERF_EF_UPDATE, and it often shares the same - subroutine as *read* with the same logic. - The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, again. -** Life cycle of these two pairs: *add* and *del* are called repeatedly as - tasks switch in-and-out; *start* and *stop* is also called when the perf core - needs a quick stop-and-start, for instance, when the interrupt period is being - adjusted. + - *stop* is called by *del* + and the perf core with flag PERF_EF_UPDATE, and it often shares the same + subroutine as *read* with the same logic. + The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, again. + + - Life cycle of these two pairs: *add* and *del* are called repeatedly as + tasks switch in-and-out; *start* and *stop* is also called when the perf core + needs a quick stop-and-start, for instance, when the interrupt period is being + adjusted. Current implementation is sufficient for now and can be easily extended to features in the future. @@ -225,25 +230,26 @@ A. Related Structures Both structures are designed to be read-only. *struct pmu* defines some function pointer interfaces, and most of them take -*struct perf_event* as a main argument, dealing with perf events according to -perf's internal state machine (check kernel/events/core.c for details). + *struct perf_event* as a main argument, dealing with perf events according to + perf's internal state machine (check kernel/events/core.c for details). *struct riscv_pmu* defines PMU-specific parameters. The naming follows the -convention of all other architectures. + convention of all other architectures. * struct perf_event: include/linux/perf_event.h * struct hw_perf_event The generic structure that represents perf events, and the hardware-related -details. + details. * struct riscv_hw_events: arch/riscv/include/asm/perf_event.h The structure that holds the status of events, has two fixed members: -the number of events and the array of the events. + the number of events and the array of the events. References ---------- [1] https://github.com/riscv/riscv-linux/pull/124 + [2] https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/f19TmCNP6yA -- 2.21.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-06-09 2:29 UTC|newest] Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-09 2:26 [PATCH v3 00/33] Convert files to ReST - part 1 Mauro Carvalho Chehab 2019-06-09 2:26 ` Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 01/33] docs: aoe: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 02/33] docs: arm64: convert docs to ReST and rename to .rst Mauro Carvalho Chehab 2019-06-09 2:26 ` Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 03/33] docs: cdrom-standard.tex: convert from LaTeX to ReST Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 04/33] docs: cdrom: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 05/33] docs: cgroup-v1: " Mauro Carvalho Chehab 2019-06-09 2:26 ` Mauro Carvalho Chehab 2019-06-11 19:03 ` Tejun Heo 2019-06-11 19:03 ` Tejun Heo 2019-06-09 2:26 ` [PATCH v3 06/33] docs: cgroup-v1/blkio-controller.rst: add a note about CFQ scheduler Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 07/33] docs: cpu-freq: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 21:38 ` Rafael J. Wysocki 2019-06-10 0:27 ` Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 08/33] docs: " Mauro Carvalho Chehab 2019-06-09 2:26 ` Mauro Carvalho Chehab 2019-06-09 2:26 ` [PATCH v3 09/33] docs: fault-injection: " Mauro Carvalho Chehab 2019-06-10 16:24 ` Federico Vaga 2019-06-09 2:27 ` [PATCH v3 10/33] docs: fb: " Mauro Carvalho Chehab 2019-06-09 7:54 ` Geert Uytterhoeven 2019-06-09 7:54 ` Geert Uytterhoeven 2019-06-09 7:54 ` Geert Uytterhoeven 2019-06-09 2:27 ` [PATCH v3 11/33] docs: fpga: " Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 12/33] docs: ide: " Mauro Carvalho Chehab 2019-06-09 7:50 ` Geert Uytterhoeven 2019-06-09 2:27 ` [PATCH v3 13/33] docs: infiniband: " Mauro Carvalho Chehab 2019-06-10 17:27 ` Jason Gunthorpe 2019-06-10 17:35 ` Jonathan Corbet 2019-06-25 13:24 ` Jason Gunthorpe 2019-06-09 2:27 ` [PATCH v3 14/33] docs: kbuild: " Mauro Carvalho Chehab 2019-06-09 2:27 ` [Bridge] " Mauro Carvalho Chehab 2019-06-09 2:27 ` [OpenRISC] " Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-10 16:25 ` Federico Vaga 2019-06-10 16:25 ` [Bridge] " Federico Vaga 2019-06-10 16:25 ` [OpenRISC] " Federico Vaga 2019-06-10 16:25 ` Federico Vaga 2019-06-10 16:48 ` Federico Vaga 2019-06-10 16:48 ` [Bridge] " Federico Vaga 2019-06-10 16:48 ` [OpenRISC] " Federico Vaga 2019-06-10 16:48 ` Federico Vaga 2019-06-09 2:27 ` [PATCH v3 15/33] docs: kdump: " Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 16/33] docs: locking: " Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-10 16:26 ` Federico Vaga 2019-06-09 2:27 ` [PATCH v3 17/33] docs: mic: " Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 18/33] docs: netlabel: " Mauro Carvalho Chehab 2019-06-12 14:48 ` Paul Moore 2019-06-09 2:27 ` [PATCH v3 19/33] docs: pcmcia: " Mauro Carvalho Chehab 2019-06-09 6:59 ` Dominik Brodowski 2019-06-09 2:27 ` [PATCH v3 20/33] docs: " Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 21/33] docs: powerpc: " Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 22/33] docs: pps.txt: convert to ReST and rename to pps.rst Mauro Carvalho Chehab 2019-06-09 9:20 ` Rodolfo Giometti 2019-06-09 2:27 ` [PATCH v3 23/33] docs: ptp.txt: convert to ReST and move to driver-api Mauro Carvalho Chehab 2019-06-09 13:45 ` Richard Cochran 2019-06-09 2:27 ` Mauro Carvalho Chehab [this message] 2019-06-09 2:27 ` [PATCH v3 24/33] docs: riscv: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 25/33] docs: Debugging390.txt: convert table to ascii artwork Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 26/33] docs: s390: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 27/33] s390: include/asm/debug.h add kerneldoc markups Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 28/33] docs: target: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 29/33] docs: timers: " Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 30/33] docs: watchdog: " Mauro Carvalho Chehab 2019-06-09 20:51 ` Guenter Roeck 2019-06-09 2:27 ` [PATCH v3 31/33] docs: xilinx: convert eemi.txt to eemi.rst Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 32/33] docs: scheduler: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab 2019-06-09 2:27 ` [PATCH v3 33/33] docs: EDID/HOWTO.txt: convert it and rename to howto.rst Mauro Carvalho Chehab 2019-06-09 2:27 ` Mauro Carvalho Chehab 2019-06-11 8:37 ` Daniel Vetter 2019-06-11 9:02 ` Mauro Carvalho Chehab 2019-06-11 9:40 ` Daniel Vetter 2019-06-11 15:37 ` Jonathan Corbet 2019-06-12 17:40 ` Mauro Carvalho Chehab 2019-06-12 19:45 ` Daniel Vetter 2019-06-09 9:16 ` [PATCH v3 00/33] Convert files to ReST - part 1 Heiko Carstens 2019-06-09 9:16 ` Heiko Carstens 2019-06-09 9:22 ` Markus Heiser 2019-06-09 9:22 ` Markus Heiser 2019-06-09 9:27 ` Heiko Carstens 2019-06-09 9:27 ` Heiko Carstens 2019-06-09 12:29 ` Mauro Carvalho Chehab 2019-06-09 12:29 ` Mauro Carvalho Chehab 2019-06-10 15:55 ` Heiko Carstens 2019-06-10 15:55 ` Heiko Carstens
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