From: "Jan Beulich" <JBeulich@suse.com>
To: xen-devel <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Keir Fraser <keir@xen.org>, Wei Liu <wei.liu2@citrix.com>
Subject: [PATCH] x86/MSI: handle both MSI-X and MSI in cfg space write intercept
Date: Thu, 21 Apr 2016 09:45:17 -0600 [thread overview]
Message-ID: <571911AD02000078000E46C9@prv-mh.provo.novell.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 1404 bytes --]
In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests")
I neglected to consider devices allowing for both MSI and MSI-X to be
used (not at the same time of course): The MSI-X part of the intercept
logic needs to fall through to the MSI one when the access is outside
the MSI-X capability bounds.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/msi.c
+++ b/xen/arch/x86/msi.c
@@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct
PCI_CAP_ID_MSIX);
ASSERT(pos);
- if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 )
- return 0;
+ if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 )
+ {
+ if ( reg != msix_control_reg(pos) || size != 2 )
+ return -EACCES;
- if ( reg != msix_control_reg(pos) || size != 2 )
- return -EACCES;
+ pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
+ if ( pdev->msix->host_maskall )
+ *data |= PCI_MSIX_FLAGS_MASKALL;
- pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
- if ( pdev->msix->host_maskall )
- *data |= PCI_MSIX_FLAGS_MASKALL;
-
- return 1;
+ return 1;
+ }
}
entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI);
[-- Attachment #2: x86-MSI-intercept-both.patch --]
[-- Type: text/plain, Size: 1465 bytes --]
x86/MSI: handle both MSI-X and MSI in cfg space write intercept
In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests")
I neglected to consider devices allowing for both MSI and MSI-X to be
used (not at the same time of course): The MSI-X part of the intercept
logic needs to fall through to the MSI one when the access is outside
the MSI-X capability bounds.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/msi.c
+++ b/xen/arch/x86/msi.c
@@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct
PCI_CAP_ID_MSIX);
ASSERT(pos);
- if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 )
- return 0;
+ if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 )
+ {
+ if ( reg != msix_control_reg(pos) || size != 2 )
+ return -EACCES;
- if ( reg != msix_control_reg(pos) || size != 2 )
- return -EACCES;
+ pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
+ if ( pdev->msix->host_maskall )
+ *data |= PCI_MSIX_FLAGS_MASKALL;
- pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
- if ( pdev->msix->host_maskall )
- *data |= PCI_MSIX_FLAGS_MASKALL;
-
- return 1;
+ return 1;
+ }
}
entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI);
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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next reply other threads:[~2016-04-21 15:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-21 15:45 Jan Beulich [this message]
2016-04-22 17:20 ` [PATCH] x86/MSI: handle both MSI-X and MSI in cfg space write intercept Andrew Cooper
2016-04-25 11:29 ` Wei Liu
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