From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH 01/11] x86/CPUID: AVX512-FP16 definitions
Date: Wed, 15 Jun 2022 12:27:32 +0200 [thread overview]
Message-ID: <5dc84e7b-e3d6-92cf-8ffb-c4bc0a3e6c74@suse.com> (raw)
In-Reply-To: <9ba3aaa7-56ce-b051-f1c4-874276e493e1@suse.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -221,6 +221,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"serialize", 0x00000007, 0, CPUID_REG_EDX, 14, 1},
{"tsxldtrk", 0x00000007, 0, CPUID_REG_EDX, 16, 1},
{"cet-ibt", 0x00000007, 0, CPUID_REG_EDX, 20, 1},
+ {"avx512-fp16", 0x00000007, 0, CPUID_REG_EDX, 23, 1},
{"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
{"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
{"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1},
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -175,6 +175,7 @@ static const char *const str_7d0[32] =
[16] = "tsxldtrk",
[18] = "pconfig",
[20] = "cet-ibt",
+ /* 22 */ [23] = "avx512-fp16",
[26] = "ibrsb", [27] = "stibp",
[28] = "l1d-flush", [29] = "arch-caps",
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -138,6 +138,7 @@
#define cpu_has_rtm_always_abort boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)
#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)
#define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE)
+#define cpu_has_avx512_fp16 boot_cpu_has(X86_FEATURE_AVX512_FP16)
#define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS)
/* CPUID level 0x00000007:1.eax */
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -281,6 +281,7 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13)
XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */
XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */
XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
+XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /* AVX512 FP16 instructions */
XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */
XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -267,7 +267,8 @@ def crunch_numbers(state):
# AVX512 extensions acting on vectors of bytes/words are made
# dependents of AVX512BW (as to requiring wider than 16-bit mask
# registers), despite the SDM not formally making this connection.
- AVX512BW: [AVX512_VBMI, AVX512_VBMI2, AVX512_BITALG, AVX512_BF16],
+ AVX512BW: [AVX512_VBMI, AVX512_VBMI2, AVX512_BITALG, AVX512_BF16,
+ AVX512_FP16],
# Extensions with VEX/EVEX encodings keyed to a separate feature
# flag are made dependents of their respective legacy feature.
next prev parent reply other threads:[~2022-06-15 10:27 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-15 10:26 [PATCH 00/11] x86: support AVX512-FP16 Jan Beulich
2022-06-15 10:27 ` Jan Beulich [this message]
2022-08-10 16:53 ` [PATCH 01/11] x86/CPUID: AVX512-FP16 definitions Andrew Cooper
2022-06-15 10:27 ` [PATCH 02/11] x86emul: handle AVX512-FP16 insns encoded in 0f3a opcode map Jan Beulich
2022-08-10 17:03 ` Andrew Cooper
2022-08-11 6:11 ` Jan Beulich
2022-06-15 10:28 ` [PATCH 03/11] x86emul: handle AVX512-FP16 Map5 arithmetic insns Jan Beulich
2022-08-10 17:41 ` Andrew Cooper
2022-06-15 10:28 ` [PATCH 04/11] x86emul: handle AVX512-FP16 move insns Jan Beulich
2022-08-10 18:04 ` Andrew Cooper
2022-08-11 6:17 ` Jan Beulich
2022-06-15 10:28 ` [PATCH 05/11] x86emul: handle AVX512-FP16 fma-like insns Jan Beulich
2022-08-10 18:14 ` Andrew Cooper
2022-08-11 6:29 ` Jan Beulich
2022-06-15 10:29 ` [PATCH 06/11] x86emul: handle AVX512-FP16 Map6 misc insns Jan Beulich
2022-08-10 18:19 ` Andrew Cooper
2022-06-15 10:29 ` [PATCH 07/11] x86emul: handle AVX512-FP16 complex multiplication insns Jan Beulich
2022-08-10 18:59 ` Andrew Cooper
2022-06-15 10:30 ` [PATCH 08/11] x86emul: handle AVX512-FP16 conversion to/from (packed) int16 insns Jan Beulich
2022-08-10 19:01 ` Andrew Cooper
2022-08-11 6:33 ` Jan Beulich
2022-06-15 10:30 ` [PATCH 09/11] x86emul: handle AVX512-FP16 floating point conversion insns Jan Beulich
2022-08-10 19:07 ` Andrew Cooper
2022-06-15 10:31 ` [PATCH 10/11] x86emul: handle AVX512-FP16 conversion to/from (packed) int{32,64} insns Jan Beulich
2022-08-10 19:09 ` Andrew Cooper
2022-08-11 6:37 ` Jan Beulich
2022-06-15 10:32 ` [PATCH 11/11] x86emul: AVX512-FP16 testing Jan Beulich
2022-08-10 19:14 ` Andrew Cooper
2022-08-11 6:43 ` Jan Beulich
2022-07-06 7:31 ` [PATCH 00/11] x86: support AVX512-FP16 Henry Wang
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