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From: Pu Wen <puwen@hygon.cn>
To: xen-devel@lists.xenproject.org
Cc: "Pu Wen" <puwen@hygon.cn>,
	"Roger Pau Monné" <roger.pau@citrix.com>,
	"Wei Liu" <wei.liu2@citrix.com>,
	"Jan Beulich" <jbeulich@suse.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>
Subject: [PATCH v3 09/14] x86/pv: Add Hygon Dhyana support to emulate MSRs access
Date: Mon, 25 Mar 2019 21:31:23 +0800	[thread overview]
Message-ID: <5e8d23e753bf24267c4f41729a2507a54c71c131.1553520193.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1553520193.git.puwen@hygon.cn>

The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
counter MSRs, hardware configuration MSR, MMIO configuration base address
MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
PV emulation infrastructure by using the code path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/pv/emul-priv-op.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 3746e2a..c92f9dc 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -924,7 +924,9 @@ static int read_msr(unsigned int reg, uint64_t *val,
             /* fall through */
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+            if ( vpmu_msr ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
             {
                 if ( vpmu_do_rdmsr(reg, val) )
                     break;
@@ -1006,7 +1008,8 @@ static int write_msr(unsigned int reg, uint64_t val,
     case MSR_K8_PSTATE6:
     case MSR_K8_PSTATE7:
     case MSR_K8_HWCR:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
              wrmsr_safe(reg, val) == 0 )
@@ -1027,8 +1030,9 @@ static int write_msr(unsigned int reg, uint64_t val,
         break;
 
     case MSR_FAM10H_MMIO_CONF_BASE:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
+        if ( (boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+              boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17) &&
+              boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             break;
         if ( !is_hardware_domain(currd) || !is_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
@@ -1067,7 +1071,8 @@ static int write_msr(unsigned int reg, uint64_t val,
     case MSR_IA32_MPERF:
     case MSR_IA32_APERF:
         if ( (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) &&
-             (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) )
+             (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) &&
+             (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
              wrmsr_safe(reg, val) == 0 )
@@ -1100,7 +1105,9 @@ static int write_msr(unsigned int reg, uint64_t val,
             vpmu_msr = true;
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+            if ( vpmu_msr ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
             {
                 if ( (vpmu_mode & XENPMU_MODE_ALL) &&
                      !is_hardware_domain(currd) )
-- 
2.7.4


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  parent reply	other threads:[~2019-03-25 13:35 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25 13:29 [PATCH v3 00/14] Add support for Hygon Dhyana Family 18h processor Pu Wen
2019-03-25 13:29 ` [PATCH v3 01/14] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2019-03-26 15:48   ` Jan Beulich
2019-03-27  8:14     ` Pu Wen
2019-03-27  8:30       ` Jan Beulich
2019-03-27 10:08         ` Pu Wen
2019-03-25 13:30 ` [PATCH v3 02/14] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 Pu Wen
2019-03-25 13:30 ` [PATCH v3 03/14] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU Pu Wen
2019-03-26 16:10   ` Jan Beulich
2019-03-27  8:16     ` Pu Wen
2019-03-27  8:37       ` Jan Beulich
2019-03-27 10:08         ` Pu Wen
2019-03-25 13:30 ` [PATCH v3 04/14] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure Pu Wen
2019-03-25 13:30 ` [PATCH v3 05/14] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery Pu Wen
2019-03-25 13:30 ` [PATCH v3 06/14] x86/apic: Add Hygon Dhyana support Pu Wen
2019-03-25 13:30 ` [PATCH v3 07/14] x86/acpi: " Pu Wen
2019-03-25 13:31 ` [PATCH v3 08/14] x86/iommu: " Pu Wen
2019-03-25 13:31 ` Pu Wen [this message]
2019-03-25 13:31 ` [PATCH v3 10/14] x86/domain: " Pu Wen
2019-03-25 13:31 ` [PATCH v3 11/14] x86/domctl: " Pu Wen
2019-03-25 13:31 ` [PATCH v3 12/14] x86/traps: " Pu Wen
2019-03-25 13:32 ` [PATCH v3 13/14] x86/cpuid: " Pu Wen
2019-03-25 13:32 ` [PATCH v3 14/14] tools/libxc: " Pu Wen

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