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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v4 2/8] target/riscv: Define ePMP mseccfg
Date: Mon, 19 Apr 2021 16:16:38 +1000	[thread overview]
Message-ID: <63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1618812899.git.alistair.francis@wdc.com>

From: Hou Weiying <weiying_hou@outlook.com>

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <SG2PR02MB2634D85E5DF0C2BB540AE1BB93450@SG2PR02MB2634.apcprd02.prod.outlook.com>
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu_bits.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8549d77b4f..24d89939a0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -220,6 +220,9 @@
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG         0x390
+#define CSR_MSECCFGH        0x391
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1
-- 
2.31.1



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com
Subject: [PATCH v4 2/8] target/riscv: Define ePMP mseccfg
Date: Mon, 19 Apr 2021 16:16:38 +1000	[thread overview]
Message-ID: <63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1618812899.git.alistair.francis@wdc.com>

From: Hou Weiying <weiying_hou@outlook.com>

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <SG2PR02MB2634D85E5DF0C2BB540AE1BB93450@SG2PR02MB2634.apcprd02.prod.outlook.com>
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu_bits.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8549d77b4f..24d89939a0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -220,6 +220,9 @@
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG         0x390
+#define CSR_MSECCFGH        0x391
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1
-- 
2.31.1



  parent reply	other threads:[~2021-04-19  6:18 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-19  6:16 [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1 Alistair Francis
2021-04-19  6:16 ` Alistair Francis
2021-04-19  6:16 ` [PATCH v4 1/8] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-04-19  6:16   ` Alistair Francis
2021-04-19  6:16 ` Alistair Francis [this message]
2021-04-19  6:16   ` [PATCH v4 2/8] target/riscv: Define ePMP mseccfg Alistair Francis
2021-04-19  6:16 ` [PATCH v4 3/8] target/riscv: Add the ePMP feature Alistair Francis
2021-04-19  6:16   ` Alistair Francis
2021-04-19  6:16 ` [PATCH v4 4/8] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-04-19  6:16   ` Alistair Francis
2021-04-19  6:17 ` [PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-04-19  6:17   ` Alistair Francis
2021-04-19  7:05   ` Bin Meng
2021-04-19  7:05     ` Bin Meng
2021-04-19  6:17 ` [PATCH v4 6/8] target/riscv: Add a config option for ePMP Alistair Francis
2021-04-19  6:17   ` Alistair Francis
2021-04-19  6:17 ` [PATCH v4 7/8] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-04-19  6:17   ` Alistair Francis
2021-04-19  6:18 ` [PATCH v4 8/8] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-04-19  6:18   ` Alistair Francis
2021-04-19 23:13 ` [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1 Alistair Francis
2021-04-19 23:13   ` Alistair Francis

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