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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com,
	alistair.francis@wdc.com, bmeng.cn@gmail.com
Subject: [Qemu-devel] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs
Date: Fri, 23 Aug 2019 08:21:09 -0700	[thread overview]
Message-ID: <6532e1a327feada5bbd0631ed6ea72ec32528936.1566573576.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1566573576.git.alistair.francis@wdc.com>

Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu_helper.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b6126af..f027be7f16 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,10 +340,8 @@ restart:
             if ((pte & PTE_X)) {
                 *prot |= PAGE_EXEC;
             }
-            /* add write permission on stores or if the page is already dirty,
-               so that we TLB miss on later writes to update the dirty bit */
-            if ((pte & PTE_W) &&
-                    (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+            /* add write permission on stores */
+            if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
                 *prot |= PAGE_WRITE;
             }
             return TRANSLATE_SUCCESS;
-- 
2.22.0



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com,
	alistair23@gmail.com, bmeng.cn@gmail.com
Subject: [Qemu-riscv] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs
Date: Fri, 23 Aug 2019 08:21:09 -0700	[thread overview]
Message-ID: <6532e1a327feada5bbd0631ed6ea72ec32528936.1566573576.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1566573576.git.alistair.francis@wdc.com>

Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu_helper.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b6126af..f027be7f16 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,10 +340,8 @@ restart:
             if ((pte & PTE_X)) {
                 *prot |= PAGE_EXEC;
             }
-            /* add write permission on stores or if the page is already dirty,
-               so that we TLB miss on later writes to update the dirty bit */
-            if ((pte & PTE_W) &&
-                    (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+            /* add write permission on stores */
+            if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
                 *prot |= PAGE_WRITE;
             }
             return TRANSLATE_SUCCESS;
-- 
2.22.0



  reply	other threads:[~2019-08-23 15:26 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-23 15:21 [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-08-23 15:21 ` [Qemu-riscv] " Alistair Francis
2019-08-23 15:21 ` Alistair Francis [this message]
2019-08-23 15:21   ` [Qemu-riscv] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-08-23 15:21   ` [Qemu-riscv] " Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-08-23 15:21   ` [Qemu-riscv] " Alistair Francis
2020-01-05 16:36   ` [Qemu-devel] " Aurelien Jarno
2020-01-05 16:36     ` Aurelien Jarno
2020-01-05 16:59     ` Aurelien Jarno
2020-01-05 16:59       ` Aurelien Jarno
2020-01-20  0:31       ` Alistair Francis
2020-01-20  0:31         ` Alistair Francis
2020-01-21 20:37         ` Aurelien Jarno
2020-01-21 20:37           ` Aurelien Jarno
2020-01-21 22:20           ` Alistair Francis
2020-01-21 22:20             ` Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-08-23 15:21   ` [Qemu-riscv] " Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 5/7] target/riscv: Use both register name and ABI name Alistair Francis
2019-08-23 15:21   ` [Qemu-riscv] " Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask Alistair Francis
2019-08-23 15:21   ` [Qemu-riscv] " Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Alistair Francis
2019-08-23 15:21   ` [Qemu-riscv] " Alistair Francis
2019-08-23 15:44   ` [Qemu-devel] " Peter Maydell
2019-08-23 15:44     ` [Qemu-riscv] " Peter Maydell
2019-08-23 15:43     ` Alistair Francis
2019-08-23 15:43       ` [Qemu-riscv] " Alistair Francis
2019-09-10 13:16   ` Palmer Dabbelt
2019-09-10 13:16     ` [Qemu-riscv] " Palmer Dabbelt
2019-09-10 13:16 ` [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 Palmer Dabbelt
2019-09-10 13:16   ` [Qemu-riscv] " Palmer Dabbelt

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