From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: horms@verge.net.au, linux-renesas-soc@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org
Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: r8a7792: remove ADSP clock
Date: Tue, 12 Jul 2016 00:52:43 +0300 [thread overview]
Message-ID: <6927311.Po2EPBmxEp@wasted.cogentembedded.com> (raw)
In-Reply-To: <1529351.Fac5N2tKoF@wasted.cogentembedded.com>
Simon Horman told me that R8A7792 had ADSP clock (based on the most recent
R-Car gen2 manual) but when I got that manual as well, this claim proved
to be false: R8A7792 is the only gen2 SoC that doesn't have ADSP at all.
Remove that clock for good...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
include/dt-bindings/clock/r8a7792-clock.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -464,7 +464,7 @@
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
- "lb", "qspi", "z", "adsp";
+ "lb", "qspi", "z";
#power-domain-cells = <0>;
};
Index: renesas/include/dt-bindings/clock/r8a7792-clock.h
===================================================================
--- renesas.orig/include/dt-bindings/clock/r8a7792-clock.h
+++ renesas/include/dt-bindings/clock/r8a7792-clock.h
@@ -18,7 +18,6 @@
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
#define R8A7792_CLK_Z 6
-#define R8A7792_CLK_ADSP 7
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0
WARNING: multiple messages have this Message-ID (diff)
From: sergei.shtylyov@cogentembedded.com (Sergei Shtylyov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: r8a7792: remove ADSP clock
Date: Tue, 12 Jul 2016 00:52:43 +0300 [thread overview]
Message-ID: <6927311.Po2EPBmxEp@wasted.cogentembedded.com> (raw)
In-Reply-To: <1529351.Fac5N2tKoF@wasted.cogentembedded.com>
Simon Horman told me that R8A7792 had ADSP clock (based on the most recent
R-Car gen2 manual) but when I got that manual as well, this claim proved
to be false: R8A7792 is the only gen2 SoC that doesn't have ADSP at all.
Remove that clock for good...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
include/dt-bindings/clock/r8a7792-clock.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -464,7 +464,7 @@
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
- "lb", "qspi", "z", "adsp";
+ "lb", "qspi", "z";
#power-domain-cells = <0>;
};
Index: renesas/include/dt-bindings/clock/r8a7792-clock.h
===================================================================
--- renesas.orig/include/dt-bindings/clock/r8a7792-clock.h
+++ renesas/include/dt-bindings/clock/r8a7792-clock.h
@@ -18,7 +18,6 @@
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
#define R8A7792_CLK_Z 6
-#define R8A7792_CLK_ADSP 7
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0
next prev parent reply other threads:[~2016-07-11 21:52 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-11 21:50 [PATCH 0/2] R8A7792 clock fixes Sergei Shtylyov
2016-07-11 21:50 ` Sergei Shtylyov
2016-07-11 21:52 ` Sergei Shtylyov [this message]
2016-07-11 21:52 ` [PATCH 2/2] ARM: dts: r8a7792: remove ADSP clock Sergei Shtylyov
2016-07-13 1:23 ` Geert Uytterhoeven
2016-07-13 1:23 ` Geert Uytterhoeven
2016-07-12 20:30 ` [PATCH 0/2] R8A7792 clock fixes Sergei Shtylyov
2016-07-12 20:30 ` Sergei Shtylyov
2016-07-15 4:25 ` Simon Horman
2016-07-15 4:25 ` Simon Horman
[not found] ` <1529351.Fac5N2tKoF-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-07-11 21:51 ` [PATCH 1/2] ARM: dts: r8a7792: add PLL1 divided by 2 clock Sergei Shtylyov
2016-07-11 21:51 ` Sergei Shtylyov
2016-07-11 21:51 ` Sergei Shtylyov
2016-07-13 1:20 ` Geert Uytterhoeven
2016-07-13 1:20 ` Geert Uytterhoeven
2016-07-13 1:20 ` Geert Uytterhoeven
2016-10-29 21:31 ` [PATCH] ARM: dts: r8a7794: remove Z clock Sergei Shtylyov
2016-10-29 21:31 ` Sergei Shtylyov
2016-10-29 21:31 ` Sergei Shtylyov
2016-11-01 9:21 ` Simon Horman
2016-11-01 9:21 ` Simon Horman
2016-11-02 8:50 ` Geert Uytterhoeven
2016-11-02 8:50 ` Geert Uytterhoeven
2016-12-14 22:07 ` [PATCH] ARM: dts: r8a7791: link DU to VSPDs Sergei Shtylyov
2016-12-14 22:07 ` Sergei Shtylyov
2016-12-14 22:07 ` Sergei Shtylyov
[not found] ` <1922293.x1RvWWSErN-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-12-15 9:59 ` Magnus Damm
2016-12-15 9:59 ` Magnus Damm
2016-12-15 9:59 ` Magnus Damm
2017-01-03 9:24 ` Laurent Pinchart
2017-01-03 9:24 ` Laurent Pinchart
2016-12-28 21:35 ` [PATCH] ARM: dts: r8a7794: link DU to VSPD Sergei Shtylyov
2016-12-28 21:35 ` Sergei Shtylyov
2016-12-28 21:35 ` Sergei Shtylyov
2017-01-03 9:24 ` Laurent Pinchart
2017-01-03 9:24 ` Laurent Pinchart
2017-01-25 21:42 ` [PATCH v2] ARM: dts: r8a7791: link DU to VSPDs Sergei Shtylyov
2017-01-25 21:42 ` Sergei Shtylyov
2017-01-26 18:42 ` Sergei Shtylyov
2017-01-26 18:42 ` Sergei Shtylyov
2017-02-01 11:13 ` Magnus Damm
2017-02-01 11:13 ` Magnus Damm
2017-02-01 11:40 ` Sergei Shtylyov
2017-02-01 11:40 ` Sergei Shtylyov
[not found] ` <4bf0b27c-9641-391d-fc05-8cdc20ce4ec3-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2017-02-01 12:01 ` Magnus Damm
2017-02-01 12:01 ` Magnus Damm
2017-02-01 12:01 ` Magnus Damm
2017-02-02 13:02 ` Sergei Shtylyov
2017-02-02 13:02 ` Sergei Shtylyov
2016-07-18 2:39 [GIT PULL] Renesas ARM Based SoC DT Fixes for v4.8 Simon Horman
2016-07-18 2:39 ` [PATCH 2/2] ARM: dts: r8a7792: remove ADSP clock Simon Horman
2016-07-18 2:39 ` Simon Horman
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