From: Johan Jonker <jbx6244@gmail.com>
To: heiko@sntech.de
Cc: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com, wxt@rock-chips.com,
kever.yang@rock-chips.com, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [RFC PATCH v1 2/2] ARM: dts: rk3288: add the interrupts property for PWM
Date: Thu, 29 Sep 2022 16:04:06 +0200 [thread overview]
Message-ID: <6eba6c10-9c96-b40f-937a-e02d43b04cd7@gmail.com> (raw)
The Rockchip rk3288 SoC has 4-built-in PWM channels.
Configurable to operate in capture mode.
Measures the high/low polarity effective cycles of this input waveform
Generates a single interrupt at the transition of input waveform polarity
Configurable to operate in continuous mode or one-shot mode.
One-shot operation will produce N + 1 periods of the waveform,
where N is the repeat counter value, and generates a single interrupt at
the end of operation.
Continuous mode generates the waveform continuously and
do not generates any interrupts.
Add interrupts property to rk3288 PWM nodes.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Original patch location:
ARM: dts: rk3288: add the interrupts property for PWM
https://github.com/rockchip-linux/kernel/commit/16b7b284618d1652e694f6286f575ce82f5f03e5
---
"rockchip,rk3288-pwm" is in use as fall back string for Rockchip SoCs with combined
PWM interrupt.
---
arch/arm/boot/dts/rk3288.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 487b0e03d..1223aa369 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -675,6 +675,7 @@
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -685,6 +686,7 @@
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
@@ -695,6 +697,7 @@
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
@@ -705,6 +708,7 @@
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Johan Jonker <jbx6244@gmail.com>
To: heiko@sntech.de
Cc: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com, wxt@rock-chips.com,
kever.yang@rock-chips.com, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [RFC PATCH v1 2/2] ARM: dts: rk3288: add the interrupts property for PWM
Date: Thu, 29 Sep 2022 16:04:06 +0200 [thread overview]
Message-ID: <6eba6c10-9c96-b40f-937a-e02d43b04cd7@gmail.com> (raw)
The Rockchip rk3288 SoC has 4-built-in PWM channels.
Configurable to operate in capture mode.
Measures the high/low polarity effective cycles of this input waveform
Generates a single interrupt at the transition of input waveform polarity
Configurable to operate in continuous mode or one-shot mode.
One-shot operation will produce N + 1 periods of the waveform,
where N is the repeat counter value, and generates a single interrupt at
the end of operation.
Continuous mode generates the waveform continuously and
do not generates any interrupts.
Add interrupts property to rk3288 PWM nodes.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Original patch location:
ARM: dts: rk3288: add the interrupts property for PWM
https://github.com/rockchip-linux/kernel/commit/16b7b284618d1652e694f6286f575ce82f5f03e5
---
"rockchip,rk3288-pwm" is in use as fall back string for Rockchip SoCs with combined
PWM interrupt.
---
arch/arm/boot/dts/rk3288.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 487b0e03d..1223aa369 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -675,6 +675,7 @@
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -685,6 +686,7 @@
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
@@ -695,6 +697,7 @@
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
@@ -705,6 +708,7 @@
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
--
2.20.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Johan Jonker <jbx6244@gmail.com>
To: heiko@sntech.de
Cc: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
sebastian.reichel@collabora.com, wxt@rock-chips.com,
kever.yang@rock-chips.com, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [RFC PATCH v1 2/2] ARM: dts: rk3288: add the interrupts property for PWM
Date: Thu, 29 Sep 2022 16:04:06 +0200 [thread overview]
Message-ID: <6eba6c10-9c96-b40f-937a-e02d43b04cd7@gmail.com> (raw)
The Rockchip rk3288 SoC has 4-built-in PWM channels.
Configurable to operate in capture mode.
Measures the high/low polarity effective cycles of this input waveform
Generates a single interrupt at the transition of input waveform polarity
Configurable to operate in continuous mode or one-shot mode.
One-shot operation will produce N + 1 periods of the waveform,
where N is the repeat counter value, and generates a single interrupt at
the end of operation.
Continuous mode generates the waveform continuously and
do not generates any interrupts.
Add interrupts property to rk3288 PWM nodes.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Original patch location:
ARM: dts: rk3288: add the interrupts property for PWM
https://github.com/rockchip-linux/kernel/commit/16b7b284618d1652e694f6286f575ce82f5f03e5
---
"rockchip,rk3288-pwm" is in use as fall back string for Rockchip SoCs with combined
PWM interrupt.
---
arch/arm/boot/dts/rk3288.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 487b0e03d..1223aa369 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -675,6 +675,7 @@
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -685,6 +686,7 @@
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
@@ -695,6 +697,7 @@
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
@@ -705,6 +708,7 @@
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2022-09-29 14:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 14:04 Johan Jonker [this message]
2022-09-29 14:04 ` [RFC PATCH v1 2/2] ARM: dts: rk3288: add the interrupts property for PWM Johan Jonker
2022-09-29 14:04 ` Johan Jonker
2022-09-29 15:50 ` Robin Murphy
2022-09-29 15:50 ` Robin Murphy
2022-09-29 15:50 ` Robin Murphy
2022-10-19 7:26 ` Uwe Kleine-König
2022-10-19 7:26 ` Uwe Kleine-König
2022-10-19 7:26 ` Uwe Kleine-König
2022-10-19 9:16 ` Heiko Stuebner
2022-10-19 9:16 ` Heiko Stuebner
2022-10-19 9:16 ` Heiko Stuebner
2022-09-30 19:55 ` Rob Herring
2022-09-30 19:55 ` Rob Herring
2022-09-30 19:55 ` Rob Herring
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