From: James Tai <james.tai@realtek.com> To: "Andreas Färber" <afaerber@suse.de> Cc: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "'DTML'" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-realtek-soc@lists.infradead.org" <linux-realtek-soc@lists.infradead.org> Subject: [PATCH v3 2/2] arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB Date: Tue, 12 Nov 2019 15:45:22 +0000 [thread overview] Message-ID: <73fb8106ec1a4665b59a2d187a576b71@realtek.com> (raw) Add Device Trees for Realtek RTD1619 SoC family, RTD1619 SoC and Realtek Mjolnir EVB. Signed-off-by: James Tai <james.tai@realtek.com> --- arch/arm64/boot/dts/realtek/Makefile | 2 + .../boot/dts/realtek/rtd1619-mjolnir.dts | 40 +++++ arch/arm64/boot/dts/realtek/rtd1619.dtsi | 12 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 163 ++++++++++++++++++ 4 files changed, 217 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1619.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd16xx.dtsi diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 555638ada721..fb5f05978ecc 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -7,3 +7,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts new file mode 100644 index 000000000000..6ab791af3896 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1619.dtsi" + +/ { + compatible = "realtek,rtd1619", "realtek,mjolnir"; + model= "Realtek Mjolnir EVB"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; /* The UART0 is debug console */ + serial1 = &uart1; /* The UART1 is on M.2 slot */ + serial2 = &uart2; /* The UART2 is on GPIO connector */ + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1619.dtsi b/arch/arm64/boot/dts/realtek/rtd1619.dtsi new file mode 100644 index 000000000000..e52bf708b04e --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include "rtd16xx.dtsi" + +/ { + compatible = "realtek,rtd1619"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi new file mode 100644 index 000000000000..d9b572a870f5 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD16xx SoC family + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/{ + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + l2: l2-cache { + compatible = "cache"; + next-level-cache = <&l3>; + + }; + + l3: l3-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "osc27M"; + #clock-cells = <0>; + }; + + soc@98000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x68000000>; + + rbus: r-bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + uart0: serial0@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial1@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial2@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <432000000>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0xc0000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>, <&cpu4>, <&cpu5>; +}; -- 2.24.0
WARNING: multiple messages have this Message-ID (diff)
From: James Tai <james.tai@realtek.com> To: "Andreas Färber" <afaerber@suse.de> Cc: Mark Rutland <mark.rutland@arm.com>, 'DTML' <devicetree@vger.kernel.org>, "linux-realtek-soc@lists.infradead.org" <linux-realtek-soc@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Subject: [PATCH v3 2/2] arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB Date: Tue, 12 Nov 2019 15:45:22 +0000 [thread overview] Message-ID: <73fb8106ec1a4665b59a2d187a576b71@realtek.com> (raw) Add Device Trees for Realtek RTD1619 SoC family, RTD1619 SoC and Realtek Mjolnir EVB. Signed-off-by: James Tai <james.tai@realtek.com> --- arch/arm64/boot/dts/realtek/Makefile | 2 + .../boot/dts/realtek/rtd1619-mjolnir.dts | 40 +++++ arch/arm64/boot/dts/realtek/rtd1619.dtsi | 12 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 163 ++++++++++++++++++ 4 files changed, 217 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1619.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd16xx.dtsi diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 555638ada721..fb5f05978ecc 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -7,3 +7,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts new file mode 100644 index 000000000000..6ab791af3896 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1619.dtsi" + +/ { + compatible = "realtek,rtd1619", "realtek,mjolnir"; + model= "Realtek Mjolnir EVB"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; /* The UART0 is debug console */ + serial1 = &uart1; /* The UART1 is on M.2 slot */ + serial2 = &uart2; /* The UART2 is on GPIO connector */ + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1619.dtsi b/arch/arm64/boot/dts/realtek/rtd1619.dtsi new file mode 100644 index 000000000000..e52bf708b04e --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include "rtd16xx.dtsi" + +/ { + compatible = "realtek,rtd1619"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi new file mode 100644 index 000000000000..d9b572a870f5 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD16xx SoC family + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/{ + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + l2: l2-cache { + compatible = "cache"; + next-level-cache = <&l3>; + + }; + + l3: l3-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "osc27M"; + #clock-cells = <0>; + }; + + soc@98000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x68000000>; + + rbus: r-bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + uart0: serial0@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial1@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial2@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <432000000>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0xc0000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>, <&cpu4>, <&cpu5>; +}; -- 2.24.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2019-11-12 15:45 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-12 15:45 James Tai [this message] 2019-11-12 15:45 ` [PATCH v3 2/2] arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB James Tai 2019-11-13 23:20 ` Andreas Färber 2019-11-13 23:20 ` Andreas Färber 2019-11-15 14:52 ` James Tai 2019-11-15 14:52 ` James Tai 2019-11-15 15:29 ` Andreas Färber 2019-11-15 15:29 ` Andreas Färber 2019-12-28 14:25 ` Andreas Färber 2019-12-28 14:25 ` Andreas Färber
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