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From: Mauro Carvalho Chehab <mchehab@kernel.org>
To: unlisted-recipients:; (no To-header on input)
Cc: "Prathap Kumar Valsan" <prathap.kumar.valsan@intel.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"David Airlie" <airlied@linux.ie>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Matt Roper" <matthew.d.roper@intel.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Michael Cheng" <michael.cheng@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org,
	"Niranjana Vishwanathapura" <niranjana.vishwanathapura@intel.com>,
	"Fei Yang" <fei.yang@intel.com>
Subject: [PATCH v2 18/21] drm/i915: Use selective tlb invalidations where supported
Date: Thu, 14 Jul 2022 13:06:23 +0100	[thread overview]
Message-ID: <7d55e7971e3f4544d8edeabb9e9c645c3042e01d.1657800199.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657800199.git.mchehab@kernel.org>

From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

[mchehab: change moved from intel_ppgtt.c to i915_vma.c]
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c       | 14 +++++++++-----
 drivers/gpu/drm/i915/i915_vma.h       |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index f764d250e929..74782fb2ccbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
 		return;
 
 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-	vma_invalidate_tlb(vm, vma_res->tlb);
+	vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5edc745dcc51..6d881a6b403a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1309,7 +1309,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
 	return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+			u64 start, u64 size)
 {
 	struct intel_gt *gt;
 	int id;
@@ -1325,9 +1326,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
 	 * the most recent TLB invalidation seqno, and if we have not yet
 	 * flushed the TLBs upon release, perform a full invalidation.
 	 */
-	for_each_gt(gt, vm->i915, id)
-		WRITE_ONCE(tlb[id],
-			   intel_gt_next_invalidate_tlb_full(vm->gt));
+	for_each_gt(gt, vm->i915, id) {
+		if (!intel_gt_invalidate_tlb_range(gt, start, size))
+			WRITE_ONCE(tlb[id],
+				   intel_gt_next_invalidate_tlb_full(vm->gt));
+	}
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -1980,7 +1983,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
 			dma_fence_put(unbind_fence);
 			unbind_fence = NULL;
 		}
-		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+				   vma->node.start, vma->size);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 33a58f605d75..3f0af9595e59 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -213,7 +213,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
 			u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+			u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"Michael Cheng" <michael.cheng@intel.com>,
	"Fei Yang" <fei.yang@intel.com>,
	"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
	"David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	linux-kernel@vger.kernel.org,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Niranjana Vishwanathapura" <niranjana.vishwanathapura@intel.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	intel-gfx@lists.freedesktop.org,
	"Prathap Kumar Valsan" <prathap.kumar.valsan@intel.com>,
	"Matthew Auld" <matthew.auld@intel.com>
Subject: [PATCH v2 18/21] drm/i915: Use selective tlb invalidations where supported
Date: Thu, 14 Jul 2022 13:06:23 +0100	[thread overview]
Message-ID: <7d55e7971e3f4544d8edeabb9e9c645c3042e01d.1657800199.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657800199.git.mchehab@kernel.org>

From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

[mchehab: change moved from intel_ppgtt.c to i915_vma.c]
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c       | 14 +++++++++-----
 drivers/gpu/drm/i915/i915_vma.h       |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index f764d250e929..74782fb2ccbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
 		return;
 
 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-	vma_invalidate_tlb(vm, vma_res->tlb);
+	vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5edc745dcc51..6d881a6b403a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1309,7 +1309,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
 	return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+			u64 start, u64 size)
 {
 	struct intel_gt *gt;
 	int id;
@@ -1325,9 +1326,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
 	 * the most recent TLB invalidation seqno, and if we have not yet
 	 * flushed the TLBs upon release, perform a full invalidation.
 	 */
-	for_each_gt(gt, vm->i915, id)
-		WRITE_ONCE(tlb[id],
-			   intel_gt_next_invalidate_tlb_full(vm->gt));
+	for_each_gt(gt, vm->i915, id) {
+		if (!intel_gt_invalidate_tlb_range(gt, start, size))
+			WRITE_ONCE(tlb[id],
+				   intel_gt_next_invalidate_tlb_full(vm->gt));
+	}
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -1980,7 +1983,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
 			dma_fence_put(unbind_fence);
 			unbind_fence = NULL;
 		}
-		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+				   vma->node.start, vma->size);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 33a58f605d75..3f0af9595e59 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -213,7 +213,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
 			u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+			u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"Michael Cheng" <michael.cheng@intel.com>,
	"David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	linux-kernel@vger.kernel.org,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	intel-gfx@lists.freedesktop.org,
	"Matthew Auld" <matthew.auld@intel.com>
Subject: [Intel-gfx] [PATCH v2 18/21] drm/i915: Use selective tlb invalidations where supported
Date: Thu, 14 Jul 2022 13:06:23 +0100	[thread overview]
Message-ID: <7d55e7971e3f4544d8edeabb9e9c645c3042e01d.1657800199.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657800199.git.mchehab@kernel.org>

From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

[mchehab: change moved from intel_ppgtt.c to i915_vma.c]
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c       | 14 +++++++++-----
 drivers/gpu/drm/i915/i915_vma.h       |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index f764d250e929..74782fb2ccbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
 		return;
 
 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-	vma_invalidate_tlb(vm, vma_res->tlb);
+	vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5edc745dcc51..6d881a6b403a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1309,7 +1309,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
 	return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+			u64 start, u64 size)
 {
 	struct intel_gt *gt;
 	int id;
@@ -1325,9 +1326,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
 	 * the most recent TLB invalidation seqno, and if we have not yet
 	 * flushed the TLBs upon release, perform a full invalidation.
 	 */
-	for_each_gt(gt, vm->i915, id)
-		WRITE_ONCE(tlb[id],
-			   intel_gt_next_invalidate_tlb_full(vm->gt));
+	for_each_gt(gt, vm->i915, id) {
+		if (!intel_gt_invalidate_tlb_range(gt, start, size))
+			WRITE_ONCE(tlb[id],
+				   intel_gt_next_invalidate_tlb_full(vm->gt));
+	}
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -1980,7 +1983,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
 			dma_fence_put(unbind_fence);
 			unbind_fence = NULL;
 		}
-		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+				   vma->node.start, vma->size);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 33a58f605d75..3f0af9595e59 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -213,7 +213,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
 			u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+			u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.36.1


  parent reply	other threads:[~2022-07-14 12:06 UTC|newest]

Thread overview: 144+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-14 12:06 [PATCH v2 00/21] Fix performance regressions with TLB and add GuC support Mauro Carvalho Chehab
2022-07-14 12:06 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06 ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 01/21] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-18 13:16   ` Tvrtko Ursulin
2022-07-18 13:16     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-18 13:16     ` Tvrtko Ursulin
2022-07-18 14:53     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-18 14:53       ` Mauro Carvalho Chehab
2022-07-18 15:01       ` Tvrtko Ursulin
2022-07-18 15:01         ` Tvrtko Ursulin
2022-07-18 15:50       ` David Laight
2022-07-18 15:50         ` David Laight
2022-07-18 15:50         ` David Laight
2022-07-19  7:24         ` Tvrtko Ursulin
2022-07-19  7:24           ` Tvrtko Ursulin
2022-07-19  7:45           ` David Laight
2022-07-19  7:45             ` David Laight
2022-07-19  7:45             ` David Laight
2022-07-22 11:56   ` Andi Shyti
2022-07-22 11:56     ` Andi Shyti
2022-07-22 11:56     ` [Intel-gfx] " Andi Shyti
2022-07-14 12:06 ` [PATCH v2 02/21] drm/i915/gt: document with_intel_gt_pm_if_awake() Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-18 13:21   ` Tvrtko Ursulin
2022-07-18 13:21     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-18 13:21     ` Tvrtko Ursulin
2022-07-14 12:06 ` [PATCH v2 03/21] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-18 13:24   ` Tvrtko Ursulin
2022-07-18 13:24     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-18 13:24     ` Tvrtko Ursulin
2022-07-22 11:57   ` Andi Shyti
2022-07-22 11:57     ` Andi Shyti
2022-07-22 11:57     ` [Intel-gfx] " Andi Shyti
2022-07-14 12:06 ` [PATCH v2 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-18 13:39   ` Tvrtko Ursulin
2022-07-18 13:39     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-18 13:39     ` Tvrtko Ursulin
2022-07-18 16:00     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-18 16:00       ` Mauro Carvalho Chehab
2022-07-22 11:58   ` Andi Shyti
2022-07-22 11:58     ` [Intel-gfx] " Andi Shyti
2022-07-22 11:58     ` Andi Shyti
2022-07-14 12:06 ` [PATCH v2 05/21] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-18 13:45   ` Tvrtko Ursulin
2022-07-18 13:45     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-18 13:45     ` Tvrtko Ursulin
2022-07-18 16:06     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-18 16:06       ` Mauro Carvalho Chehab
2022-07-19  7:19       ` Tvrtko Ursulin
2022-07-19  7:19         ` Tvrtko Ursulin
2022-07-22 12:00   ` Andi Shyti
2022-07-22 12:00     ` [Intel-gfx] " Andi Shyti
2022-07-22 12:00     ` Andi Shyti
2022-07-14 12:06 ` [PATCH v2 06/21] drm/i915/gt: Batch TLB invalidations Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-18 13:52   ` Tvrtko Ursulin
2022-07-18 13:52     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-18 13:52     ` Tvrtko Ursulin
2022-07-20  7:13     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-20  7:13       ` Mauro Carvalho Chehab
2022-07-20 10:49       ` Tvrtko Ursulin
2022-07-20 10:49         ` Tvrtko Ursulin
2022-07-20 10:54   ` Tvrtko Ursulin
2022-07-20 10:54     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-20 10:54     ` Tvrtko Ursulin
2022-07-27 11:48     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-27 11:48       ` Mauro Carvalho Chehab
2022-07-27 12:56       ` Tvrtko Ursulin
2022-07-27 12:56         ` Tvrtko Ursulin
2022-07-28  6:32         ` Mauro Carvalho Chehab
2022-07-28  6:32           ` Mauro Carvalho Chehab
2022-07-28  7:26           ` Mauro Carvalho Chehab
2022-07-28  7:26             ` Mauro Carvalho Chehab
2022-07-28 10:11           ` Tvrtko Ursulin
2022-07-28 10:11             ` Tvrtko Ursulin
2022-07-14 12:06 ` [PATCH v2 07/21] drm/i915/gt: describe the new tlb parameter at i915_vma_resource Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 08/21] drm/i915/gt: Move TLB invalidation to its own file Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-22 12:07   ` Andi Shyti
2022-07-22 12:07     ` [Intel-gfx] " Andi Shyti
2022-07-22 12:07     ` Andi Shyti
2022-07-14 12:06 ` [PATCH v2 09/21] drm/i915/guc: Define CTB based TLB invalidation routines Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 14:06   ` Michal Wajdeczko
2022-07-14 14:06     ` [Intel-gfx] " Michal Wajdeczko
2022-07-14 14:06     ` Michal Wajdeczko
2022-08-02  7:48     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-08-02  7:48       ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 10/21] drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 11/21] drm/i915/guc: document the TLB invalidation struct members Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 12/21] drm/i915/guc: Introduce TLB_INVALIDATION_ALL action Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 13/21] drm/i915: Invalidate the TLBs on each GT Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 14/21] drm/i915: document tlb field at struct drm_i915_gem_object Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 15/21] drm/i915: Add platform macro for selective tlb flush Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 16/21] drm/i915: Define GuC Based TLB invalidation routines Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 15:20   ` Michal Wajdeczko
2022-07-14 15:20     ` [Intel-gfx] " Michal Wajdeczko
2022-07-14 15:20     ` Michal Wajdeczko
2022-07-14 12:06 ` [PATCH v2 17/21] drm/i915: Add generic interface for tlb invalidation for XeHP Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06 ` Mauro Carvalho Chehab [this message]
2022-07-14 12:06   ` [Intel-gfx] [PATCH v2 18/21] drm/i915: Use selective tlb invalidations where supported Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 19/21] drm/i915/gt: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 20/21] drm/i915/guc: describe enum intel_guc_tlb_invalidation_type Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:06 ` [PATCH v2 21/21] drm/i915/guc: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-14 12:06   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-14 12:06   ` Mauro Carvalho Chehab
2022-07-14 12:27 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support (rev3) Patchwork
2022-07-28  8:01 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support (rev4) Patchwork

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