From: Christophe Leroy <christophe.leroy@c-s.fr> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, npiggin@gmail.com, dja@axtens.net Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mm@kvack.org Subject: [PATCH v3 09/15] powerpc/8xx: Use alternative scratch registers in DTLB miss handler Date: Tue, 10 Sep 2019 09:16:28 +0000 (UTC) [thread overview] Message-ID: <7d8bd54fcdd927cbe492a9178f7dc7ca136f9238.1568106758.git.christophe.leroy@c-s.fr> (raw) In-Reply-To: <cover.1568106758.git.christophe.leroy@c-s.fr> In preparation of handling CONFIG_VMAP_STACK, DTLB miss handler need to use different scratch registers than other exception handlers in order to not jeopardise exception entry on stack DTLB misses. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- arch/powerpc/kernel/head_8xx.S | 27 ++++++++++++++------------- arch/powerpc/perf/8xx-pmu.c | 12 ++++++++---- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 25e19af49705..3de9c5f1746c 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -193,8 +193,9 @@ SystemCall: 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) addi r10, r10, 1 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) - mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 + mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi #endif @@ -337,8 +338,8 @@ ITLBMissLinear: . = 0x1200 DataStoreTLBMiss: - mtspr SPRN_SPRG_SCRATCH0, r10 - mtspr SPRN_SPRG_SCRATCH1, r11 + mtspr SPRN_DAR, r10 + mtspr SPRN_M_TW, r11 mfcr r11 /* If we are faulting a kernel address, we have to use the @@ -403,10 +404,10 @@ DataStoreTLBMiss: mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ /* Restore registers */ - mtspr SPRN_DAR, r11 /* Tag DAR */ -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 +0: mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi patch_site 0b, patch__dtlbmiss_exit_1 @@ -422,10 +423,10 @@ DTLBMissIMMR: mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ li r11, RPN_PATTERN - mtspr SPRN_DAR, r11 /* Tag DAR */ -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 +0: mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi patch_site 0b, patch__dtlbmiss_exit_2 @@ -459,10 +460,10 @@ DTLBMissLinear: mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ li r11, RPN_PATTERN - mtspr SPRN_DAR, r11 /* Tag DAR */ -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 +0: mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi patch_site 0b, patch__dtlbmiss_exit_3 diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c index 19124b0b171a..1ad03c55c88c 100644 --- a/arch/powerpc/perf/8xx-pmu.c +++ b/arch/powerpc/perf/8xx-pmu.c @@ -157,10 +157,6 @@ static void mpc8xx_pmu_read(struct perf_event *event) static void mpc8xx_pmu_del(struct perf_event *event, int flags) { - /* mfspr r10, SPRN_SPRG_SCRATCH0 */ - unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) | - __PPC_SPR(SPRN_SPRG_SCRATCH0); - mpc8xx_pmu_read(event); /* If it was the last user, stop counting to avoid useles overhead */ @@ -173,6 +169,10 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) break; case PERF_8xx_ID_ITLB_LOAD_MISS: if (atomic_dec_return(&itlb_miss_ref) == 0) { + /* mfspr r10, SPRN_SPRG_SCRATCH0 */ + unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) | + __PPC_SPR(SPRN_SPRG_SCRATCH0); + patch_instruction_site(&patch__itlbmiss_exit_1, insn); #ifndef CONFIG_PIN_TLB_TEXT patch_instruction_site(&patch__itlbmiss_exit_2, insn); @@ -181,6 +181,10 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) break; case PERF_8xx_ID_DTLB_LOAD_MISS: if (atomic_dec_return(&dtlb_miss_ref) == 0) { + /* mfspr r10, SPRN_DAR */ + unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) | + __PPC_SPR(SPRN_DAR); + patch_instruction_site(&patch__dtlbmiss_exit_1, insn); patch_instruction_site(&patch__dtlbmiss_exit_2, insn); patch_instruction_site(&patch__dtlbmiss_exit_3, insn); -- 2.13.3
WARNING: multiple messages have this Message-ID (diff)
From: Christophe Leroy <christophe.leroy@c-s.fr> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, npiggin@gmail.com, dja@axtens.net Cc: linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 09/15] powerpc/8xx: Use alternative scratch registers in DTLB miss handler Date: Tue, 10 Sep 2019 09:16:28 +0000 (UTC) [thread overview] Message-ID: <7d8bd54fcdd927cbe492a9178f7dc7ca136f9238.1568106758.git.christophe.leroy@c-s.fr> (raw) In-Reply-To: <cover.1568106758.git.christophe.leroy@c-s.fr> In preparation of handling CONFIG_VMAP_STACK, DTLB miss handler need to use different scratch registers than other exception handlers in order to not jeopardise exception entry on stack DTLB misses. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- arch/powerpc/kernel/head_8xx.S | 27 ++++++++++++++------------- arch/powerpc/perf/8xx-pmu.c | 12 ++++++++---- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 25e19af49705..3de9c5f1746c 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -193,8 +193,9 @@ SystemCall: 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) addi r10, r10, 1 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) - mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 + mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi #endif @@ -337,8 +338,8 @@ ITLBMissLinear: . = 0x1200 DataStoreTLBMiss: - mtspr SPRN_SPRG_SCRATCH0, r10 - mtspr SPRN_SPRG_SCRATCH1, r11 + mtspr SPRN_DAR, r10 + mtspr SPRN_M_TW, r11 mfcr r11 /* If we are faulting a kernel address, we have to use the @@ -403,10 +404,10 @@ DataStoreTLBMiss: mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ /* Restore registers */ - mtspr SPRN_DAR, r11 /* Tag DAR */ -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 +0: mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi patch_site 0b, patch__dtlbmiss_exit_1 @@ -422,10 +423,10 @@ DTLBMissIMMR: mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ li r11, RPN_PATTERN - mtspr SPRN_DAR, r11 /* Tag DAR */ -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 +0: mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi patch_site 0b, patch__dtlbmiss_exit_2 @@ -459,10 +460,10 @@ DTLBMissLinear: mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ li r11, RPN_PATTERN - mtspr SPRN_DAR, r11 /* Tag DAR */ -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 +0: mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW rfi patch_site 0b, patch__dtlbmiss_exit_3 diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c index 19124b0b171a..1ad03c55c88c 100644 --- a/arch/powerpc/perf/8xx-pmu.c +++ b/arch/powerpc/perf/8xx-pmu.c @@ -157,10 +157,6 @@ static void mpc8xx_pmu_read(struct perf_event *event) static void mpc8xx_pmu_del(struct perf_event *event, int flags) { - /* mfspr r10, SPRN_SPRG_SCRATCH0 */ - unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) | - __PPC_SPR(SPRN_SPRG_SCRATCH0); - mpc8xx_pmu_read(event); /* If it was the last user, stop counting to avoid useles overhead */ @@ -173,6 +169,10 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) break; case PERF_8xx_ID_ITLB_LOAD_MISS: if (atomic_dec_return(&itlb_miss_ref) == 0) { + /* mfspr r10, SPRN_SPRG_SCRATCH0 */ + unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) | + __PPC_SPR(SPRN_SPRG_SCRATCH0); + patch_instruction_site(&patch__itlbmiss_exit_1, insn); #ifndef CONFIG_PIN_TLB_TEXT patch_instruction_site(&patch__itlbmiss_exit_2, insn); @@ -181,6 +181,10 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) break; case PERF_8xx_ID_DTLB_LOAD_MISS: if (atomic_dec_return(&dtlb_miss_ref) == 0) { + /* mfspr r10, SPRN_DAR */ + unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) | + __PPC_SPR(SPRN_DAR); + patch_instruction_site(&patch__dtlbmiss_exit_1, insn); patch_instruction_site(&patch__dtlbmiss_exit_2, insn); patch_instruction_site(&patch__dtlbmiss_exit_3, insn); -- 2.13.3
next prev parent reply other threads:[~2019-09-10 9:17 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-09-10 9:16 [PATCH v3 00/15] Enable CONFIG_VMAP_STACK on PPC32 Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 01/15] powerpc/32: replace MTMSRD() by mtmsr Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 02/15] powerpc/32: Add EXCEPTION_PROLOG_0 in head_32.h Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 03/15] powerpc/32: save DEAR/DAR before calling handle_page_fault Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 04/15] powerpc/32: move MSR_PR test into EXCEPTION_PROLOG_0 Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 05/15] powerpc/32: add a macro to get and/or save DAR and DSISR on stack Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 06/15] powerpc/32: prepare for CONFIG_VMAP_STACK Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-10-17 7:36 ` Andrew Donnellan 2019-10-17 7:36 ` Andrew Donnellan 2019-10-18 6:46 ` Christophe Leroy 2019-10-18 6:46 ` Christophe Leroy 2019-10-18 7:09 ` Andrew Donnellan 2019-10-18 7:09 ` Andrew Donnellan 2019-09-10 9:16 ` [PATCH v3 07/15] powerpc: align stack to 2 * THREAD_SIZE with VMAP_STACK Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 08/15] powerpc/32: Add early stack overflow detection with VMAP stack Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy [this message] 2019-09-10 9:16 ` [PATCH v3 09/15] powerpc/8xx: Use alternative scratch registers in DTLB miss handler Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 10/15] powerpc/8xx: drop exception entries for non-existing exceptions Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 11/15] powerpc/8xx: move DataStoreTLBMiss perf handler Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 12/15] powerpc/8xx: split breakpoint exception Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 13/15] powerpc/8xx: Enable CONFIG_VMAP_STACK Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 14/15] powerpc/32s: reorganise DSI handler Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-09-10 9:16 ` [PATCH v3 15/15] powerpc/32s: Activate CONFIG_VMAP_STACK Christophe Leroy 2019-09-10 9:16 ` Christophe Leroy 2019-11-18 11:11 ` Michael Ellerman 2019-11-18 11:11 ` Michael Ellerman 2019-11-19 6:57 ` Michael Ellerman 2019-11-19 6:57 ` Michael Ellerman 2019-11-19 17:23 ` Christophe Leroy 2019-11-19 17:23 ` Christophe Leroy 2019-11-19 6:58 ` Michael Ellerman 2019-11-19 6:58 ` Michael Ellerman 2019-11-20 7:38 ` Christophe Leroy 2019-11-20 7:38 ` Christophe Leroy 2019-11-26 9:01 ` Christophe Leroy 2019-11-26 9:01 ` Christophe Leroy
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=7d8bd54fcdd927cbe492a9178f7dc7ca136f9238.1568106758.git.christophe.leroy@c-s.fr \ --to=christophe.leroy@c-s.fr \ --cc=benh@kernel.crashing.org \ --cc=dja@axtens.net \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mm@kvack.org \ --cc=linuxppc-dev@lists.ozlabs.org \ --cc=mpe@ellerman.id.au \ --cc=npiggin@gmail.com \ --cc=paulus@samba.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.