From: Thomas Gleixner <tglx@linutronix.de>
To: Daniel Vacek <neelx@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, open list <linux-kernel@vger.kernel.org>
Subject: [PATCH] x86/apic: Clarify i82489DX bit overlap in APIC_LVT0
Date: Tue, 12 Apr 2022 22:34:21 +0200 [thread overview]
Message-ID: <87ee22f3ci.ffs@tglx> (raw)
In-Reply-To: <CACjP9X_A7aLmvypyOz1UrXM571gx_X5q7=w-1j+G+MSbCteiEw@mail.gmail.com>
Daniel stumbled over the undocumented bit overlap of the i82498DX external
APIC and the TSC deadline timer configuration bit in modern APICs.
Remove the i82489DX macro maze, use a i82489DX specific define in the apic
code and document the overlap in a comment.
Reported-by: Daniel Vacek <neelx@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/apicdef.h | 6 ------
arch/x86/kernel/apic/apic.c | 11 ++++++++++-
2 files changed, 10 insertions(+), 7 deletions(-)
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -95,12 +95,6 @@
#define APIC_LVTTHMR 0x330
#define APIC_LVTPC 0x340
#define APIC_LVT0 0x350
-#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
-#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
-#define SET_APIC_TIMER_BASE(x) (((x) << 18))
-#define APIC_TIMER_BASE_CLKIN 0x0
-#define APIC_TIMER_BASE_TMBASE 0x1
-#define APIC_TIMER_BASE_DIV 0x2
#define APIC_LVT_TIMER_ONESHOT (0 << 17)
#define APIC_LVT_TIMER_PERIODIC (1 << 17)
#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -320,6 +320,9 @@ int lapic_get_maxlvt(void)
#define APIC_DIVISOR 16
#define TSC_DIVISOR 8
+/* i82489DX specific */
+#define I82489DX_BASE_DIVIDER (((0x2) << 18))
+
/*
* This function sets up the local APIC timer, with a timeout of
* 'clocks' APIC bus clock. During calibration we actually call
@@ -340,8 +343,14 @@ static void __setup_APIC_LVTT(unsigned i
else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
+ /*
+ * The i82489DX APIC uses bit 18 and 19 for the base divider. This
+ * overlaps with bit 18 on integrated APICs, but is not documented
+ * in the SDM. No problem though. i82489DX equipped systems do not
+ * have TSC deadline timer.
+ */
if (!lapic_is_integrated())
- lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
+ lvtt_value |= I82489DX_BASE_DIVIDER;
if (!irqen)
lvtt_value |= APIC_LVT_MASKED;
next prev parent reply other threads:[~2022-04-12 20:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 14:02 [PATCH] [RFC] apic: fix timer base macro definitions Daniel Vacek
2022-04-06 11:47 ` Thomas Gleixner
2022-04-06 14:54 ` Daniel Vacek
2022-04-12 20:34 ` Thomas Gleixner [this message]
2022-04-12 22:17 ` [PATCH] x86/apic: Clarify i82489DX bit overlap in APIC_LVT0 Maciej W. Rozycki
2022-04-13 13:24 ` Thomas Gleixner
2022-04-13 15:55 ` Maciej W. Rozycki
2022-04-13 16:44 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
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