From: James Hogan <james.hogan@imgtec.com> To: <linux-mips@linux-mips.org>, <kvm@vger.kernel.org> Cc: "James Hogan" <james.hogan@imgtec.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Ralf Baechle" <ralf@linux-mips.org>, "David Daney" <david.daney@cavium.com>, "Andreas Herrmann" <andreas.herrmann@caviumnetworks.com> Subject: [PATCH 4/8] KVM: MIPS/T&E: Report correct dcache line size Date: Tue, 14 Mar 2017 10:25:47 +0000 [thread overview] Message-ID: <8d3b879d1550f684cd780f3134e9799e026d4e85.1489486985.git-series.james.hogan@imgtec.com> (raw) In-Reply-To: <cover.79b3feae3a98cb166c2d40a7bd4e854a5faedc89.1489486985.git-series.james.hogan@imgtec.com> Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL, so encode the correct value for the guest CP0_Config1.DL based on cpu_dcache_line_size(). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/kvm/trap_emul.c | 8 ++++++++ 1 file changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c index 75ba3c4b7cd5..a563759fd142 100644 --- a/arch/mips/kvm/trap_emul.c +++ b/arch/mips/kvm/trap_emul.c @@ -12,6 +12,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/kvm_host.h> +#include <linux/log2.h> #include <linux/uaccess.h> #include <linux/vmalloc.h> #include <asm/mmu_context.h> @@ -644,6 +645,13 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu) /* Read the cache characteristics from the host Config1 Register */ config1 = (read_c0_config1() & ~0x7f); + /* DCache line size not correctly reported in Config1 on Octeon CPUs */ + if (cpu_dcache_line_size()) { + config1 &= ~MIPS_CONF1_DL; + config1 |= ((ilog2(cpu_dcache_line_size()) - 1) << + MIPS_CONF1_DL_SHF) & MIPS_CONF1_DL; + } + /* Set up MMU size */ config1 &= ~(0x3f << 25); config1 |= ((KVM_MIPS_GUEST_TLB_SIZE - 1) << 25); -- git-series 0.8.10
WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com> To: linux-mips@linux-mips.org, kvm@vger.kernel.org Cc: "James Hogan" <james.hogan@imgtec.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Ralf Baechle" <ralf@linux-mips.org>, "David Daney" <david.daney@cavium.com>, "Andreas Herrmann" <andreas.herrmann@caviumnetworks.com> Subject: [PATCH 4/8] KVM: MIPS/T&E: Report correct dcache line size Date: Tue, 14 Mar 2017 10:25:47 +0000 [thread overview] Message-ID: <8d3b879d1550f684cd780f3134e9799e026d4e85.1489486985.git-series.james.hogan@imgtec.com> (raw) Message-ID: <20170314102547.Xe8-d_75W20cSiVedYSQDUwxKx1O1Z3hUF5y1bvUqvU@z> (raw) In-Reply-To: <cover.79b3feae3a98cb166c2d40a7bd4e854a5faedc89.1489486985.git-series.james.hogan@imgtec.com> Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL, so encode the correct value for the guest CP0_Config1.DL based on cpu_dcache_line_size(). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/kvm/trap_emul.c | 8 ++++++++ 1 file changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c index 75ba3c4b7cd5..a563759fd142 100644 --- a/arch/mips/kvm/trap_emul.c +++ b/arch/mips/kvm/trap_emul.c @@ -12,6 +12,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/kvm_host.h> +#include <linux/log2.h> #include <linux/uaccess.h> #include <linux/vmalloc.h> #include <asm/mmu_context.h> @@ -644,6 +645,13 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu) /* Read the cache characteristics from the host Config1 Register */ config1 = (read_c0_config1() & ~0x7f); + /* DCache line size not correctly reported in Config1 on Octeon CPUs */ + if (cpu_dcache_line_size()) { + config1 &= ~MIPS_CONF1_DL; + config1 |= ((ilog2(cpu_dcache_line_size()) - 1) << + MIPS_CONF1_DL_SHF) & MIPS_CONF1_DL; + } + /* Set up MMU size */ config1 &= ~(0x3f << 25); config1 |= ((KVM_MIPS_GUEST_TLB_SIZE - 1) << 25); -- git-series 0.8.10
next prev parent reply other threads:[~2017-03-14 10:34 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-14 10:25 [PATCH 0/8] KVM: MIPS: Add Cavium Octeon III support James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-14 10:25 ` [PATCH 1/8] MIPS: Add Octeon III register accessors & definitions James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-15 13:41 ` Ralf Baechle 2017-03-16 13:11 ` James Hogan 2017-03-14 10:25 ` [PATCH 2/8] KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-14 10:25 ` [PATCH 3/8] KVM: MIPS/TLB: Handle virtually tagged icaches James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-14 10:25 ` James Hogan [this message] 2017-03-14 10:25 ` [PATCH 4/8] KVM: MIPS/T&E: Report correct dcache line size James Hogan 2017-03-14 10:25 ` [PATCH 5/8] KVM: MIPS/VZ: VZ hardware setup for Octeon III James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-14 10:25 ` [PATCH 6/8] KVM: MIPS/VZ: Emulate hit CACHE ops " James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-14 10:25 ` [PATCH 7/8] KVM: MIPS/VZ: Handle Octeon III guest.PRid register James Hogan 2017-03-14 10:25 ` James Hogan 2017-03-14 10:25 ` [PATCH 8/8] MIPS: Allow KVM to be enabled on Octeon CPUs James Hogan 2017-03-14 10:25 ` James Hogan
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