All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
	"Fei Yang" <fei.yang@intel.com>,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	"Andi Shyti" <andi.shyti@linux.intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-gfx@lists.freedesktop.org,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
	mauro.chehab@linux.intel.com,
	"Michał Winiarski" <michal.winiarski@intel.com>,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org,
	"John Harrison" <John.C.Harrison@Intel.com>
Subject: [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged
Date: Wed, 15 Jun 2022 16:27:37 +0100	[thread overview]
Message-ID: <9d9e663ca8e97becf04e1d4c8cb8a9a1f397a5f1.1655306128.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1655306128.git.mchehab@kernel.org>

From: Chris Wilson <chris.p.wilson@intel.com>

Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.

Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 61b7ec5118f9..fb4fd5273ca4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1226,6 +1226,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 	if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
 		return;
 
+	if (intel_gt_is_wedged(gt))
+		return;
+
 	if (GRAPHICS_VER(i915) == 12) {
 		regs = gen12_regs;
 		num = ARRAY_SIZE(gen12_regs);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-gfx@lists.freedesktop.org,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	mauro.chehab@linux.intel.com,
	"Michał Winiarski" <michal.winiarski@intel.com>,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged
Date: Wed, 15 Jun 2022 16:27:37 +0100	[thread overview]
Message-ID: <9d9e663ca8e97becf04e1d4c8cb8a9a1f397a5f1.1655306128.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1655306128.git.mchehab@kernel.org>

From: Chris Wilson <chris.p.wilson@intel.com>

Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.

Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 61b7ec5118f9..fb4fd5273ca4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1226,6 +1226,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 	if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
 		return;
 
+	if (intel_gt_is_wedged(gt))
+		return;
+
 	if (GRAPHICS_VER(i915) == 12) {
 		regs = gen12_regs;
 		num = ARRAY_SIZE(gen12_regs);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
To: unlisted-recipients:; (no To-header on input)
Cc: "Chris Wilson" <chris.p.wilson@intel.com>,
	"Fei Yang" <fei.yang@intel.com>,
	"Michał Winiarski" <michal.winiarski@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Andi Shyti" <andi.shyti@linux.intel.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	"David Airlie" <airlied@linux.ie>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	"John Harrison" <John.C.Harrison@Intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	"Matt Roper" <matthew.d.roper@intel.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com,
	stable@vger.kernel.org,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>
Subject: [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged
Date: Wed, 15 Jun 2022 16:27:37 +0100	[thread overview]
Message-ID: <9d9e663ca8e97becf04e1d4c8cb8a9a1f397a5f1.1655306128.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1655306128.git.mchehab@kernel.org>

From: Chris Wilson <chris.p.wilson@intel.com>

Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.

Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 61b7ec5118f9..fb4fd5273ca4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1226,6 +1226,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 	if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
 		return;
 
+	if (intel_gt_is_wedged(gt))
+		return;
+
 	if (GRAPHICS_VER(i915) == 12) {
 		regs = gen12_regs;
 		num = ARRAY_SIZE(gen12_regs);
-- 
2.36.1


  parent reply	other threads:[~2022-06-15 15:28 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-15 15:27 [PATCH 0/6] Fix TLB invalidate issues with Broadwell Mauro Carvalho Chehab
2022-06-15 15:27 ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:21   ` Tvrtko Ursulin
2022-06-16  7:21     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:21     ` Tvrtko Ursulin
2022-06-23 11:04   ` Andi Shyti
2022-06-23 11:04     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:04     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 2/6] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-15 17:03   ` Umesh Nerlige Ramappa
2022-06-15 17:03     ` Umesh Nerlige Ramappa
2022-06-23 11:07   ` Andi Shyti
2022-06-23 11:07     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:07     ` Andi Shyti
2022-06-15 15:27 ` Mauro Carvalho Chehab [this message]
2022-06-15 15:27   ` [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:25   ` Tvrtko Ursulin
2022-06-16  7:25     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:25     ` Tvrtko Ursulin
2022-06-23 11:08   ` Andi Shyti
2022-06-23 11:08     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:08     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:33   ` Tvrtko Ursulin
2022-06-16  7:33     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:33     ` Tvrtko Ursulin
2022-06-23 11:13   ` Andi Shyti
2022-06-23 11:13     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:13     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:35   ` Tvrtko Ursulin
2022-06-16  7:35     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:35     ` Tvrtko Ursulin
2022-06-23 11:17   ` Andi Shyti
2022-06-23 11:17     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:17     ` Andi Shyti
2022-06-24  8:34     ` Tvrtko Ursulin
2022-06-24  8:34       ` [Intel-gfx] " Tvrtko Ursulin
2022-06-24  8:34       ` Tvrtko Ursulin
2022-06-27  9:00       ` Mauro Carvalho Chehab
2022-06-27  9:00         ` Mauro Carvalho Chehab
2022-06-27  9:00         ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-28 15:49         ` Tvrtko Ursulin
2022-06-28 15:49           ` [Intel-gfx] " Tvrtko Ursulin
2022-06-28 15:49           ` Tvrtko Ursulin
2022-06-29 15:30           ` Mauro Carvalho Chehab
2022-06-29 15:30             ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-29 15:30             ` Mauro Carvalho Chehab
2022-06-29 16:02             ` Tvrtko Ursulin
2022-06-29 16:02               ` Tvrtko Ursulin
2022-06-29 16:02               ` [Intel-gfx] " Tvrtko Ursulin
2022-06-30  7:32               ` Mauro Carvalho Chehab
2022-06-30  7:32                 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-30  7:32                 ` Mauro Carvalho Chehab
2022-06-30  8:12                 ` Tvrtko Ursulin
2022-06-30  8:12                   ` Tvrtko Ursulin
2022-06-30  8:12                   ` [Intel-gfx] " Tvrtko Ursulin
2022-06-30 16:01                   ` Mauro Carvalho Chehab
2022-06-30 16:01                     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-30 16:01                     ` Mauro Carvalho Chehab
2022-07-01  7:56                     ` Tvrtko Ursulin
2022-07-01  7:56                       ` [Intel-gfx] " Tvrtko Ursulin
2022-07-01  7:56                       ` Tvrtko Ursulin
2022-07-04  8:42                       ` Mauro Carvalho Chehab
2022-07-04  8:42                         ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-04  8:42                         ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-23 11:18   ` Andi Shyti
2022-06-23 11:18     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:18     ` Andi Shyti
2022-06-15 17:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix TLB invalidate issues with Broadwell Patchwork
2022-06-15 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-15 17:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-15 23:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9d9e663ca8e97becf04e1d4c8cb8a9a1f397a5f1.1655306128.git.mchehab@kernel.org \
    --to=mchehab@kernel.org \
    --cc=John.C.Harrison@Intel.com \
    --cc=airlied@linux.ie \
    --cc=airlied@redhat.com \
    --cc=andi.shyti@linux.intel.com \
    --cc=chris.p.wilson@intel.com \
    --cc=daniele.ceraolospurio@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=fei.yang@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=lucas.demarchi@intel.com \
    --cc=matthew.auld@intel.com \
    --cc=mauro.chehab@linux.intel.com \
    --cc=michal.winiarski@intel.com \
    --cc=rodrigo.vivi@intel.com \
    --cc=stable@vger.kernel.org \
    --cc=thomas.hellstrom@intel.com \
    --cc=thomas.hellstrom@linux.intel.com \
    --cc=tvrtko.ursulin@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.