From: Doug Anderson <dianders@chromium.org> To: Sharat Masetty <smasetty@codeaurora.org> Cc: freedreno <freedreno@lists.freedesktop.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, dri-devel@freedesktop.org, linux-arm-msm <linux-arm-msm@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Jordan Crouse <jcrouse@codeaurora.org>, Matthias Kaehlcke <mka@chromium.org> Subject: Re: [PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob Date: Wed, 5 Feb 2020 11:19:33 -0800 [thread overview] Message-ID: <CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com> (raw) In-Reply-To: <1580886097-6312-4-git-send-email-smasetty@codeaurora.org> Hi, On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty <smasetty@codeaurora.org> wrote: > > This patch adds the required dt nodes and properties > to enabled A618 GPU. > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ > 1 file changed, 102 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index f3fcc5c..63fff15 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1043,6 +1043,108 @@ > }; > }; > > + gpu: gpu@5000000 { > + compatible = "qcom,adreno-618.0", "qcom,adreno"; > + #stream-id-cells = <16>; > + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, > + <0 0x05061000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&adreno_smmu 0>; > + operating-points-v2 = <&gpu_opp_table>; > + qcom,gmu = <&gmu>; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + }; > + > + opp-565000000 { > + opp-hz = /bits/ 64 <565000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + }; > + > + opp-430000000 { > + opp-hz = /bits/ 64 <430000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + }; > + > + opp-355000000 { > + opp-hz = /bits/ 64 <355000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + }; > + > + opp-267000000 { > + opp-hz = /bits/ 64 <267000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + }; > + > + opp-180000000 { > + opp-hz = /bits/ 64 <180000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; > + }; > + }; > + }; > + > + adreno_smmu: iommu@5040000 { > + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; As per prior discussion "qcom,sc7180-smmu-v2" needs to be added to the bindings. > + reg = <0 0x05040000 0 0x10000>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>; > + > + clock-names = "bus", "iface", "mem_iface_clk"; As per discussion in v3 [1], "mem_iface_clk" is new and needs to be added to the bindings. Presumably that patch should be posted / Acked by Rob before we land this dts. Other than relying on un-posted bindings, this looks sane to me and this patch lets me bring the GPU up on my sc7180-based board. Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> -Doug [1] https://lore.kernel.org/r/1e29097cc1cdf18671379f6420f872b0@codeaurora.org
WARNING: multiple messages have this Message-ID (diff)
From: Doug Anderson <dianders@chromium.org> To: Sharat Masetty <smasetty@codeaurora.org> Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-arm-msm <linux-arm-msm@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Matthias Kaehlcke <mka@chromium.org>, dri-devel@freedesktop.org, freedreno <freedreno@lists.freedesktop.org> Subject: Re: [PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob Date: Wed, 5 Feb 2020 11:19:33 -0800 [thread overview] Message-ID: <CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com> (raw) In-Reply-To: <1580886097-6312-4-git-send-email-smasetty@codeaurora.org> Hi, On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty <smasetty@codeaurora.org> wrote: > > This patch adds the required dt nodes and properties > to enabled A618 GPU. > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ > 1 file changed, 102 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index f3fcc5c..63fff15 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1043,6 +1043,108 @@ > }; > }; > > + gpu: gpu@5000000 { > + compatible = "qcom,adreno-618.0", "qcom,adreno"; > + #stream-id-cells = <16>; > + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, > + <0 0x05061000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&adreno_smmu 0>; > + operating-points-v2 = <&gpu_opp_table>; > + qcom,gmu = <&gmu>; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + }; > + > + opp-565000000 { > + opp-hz = /bits/ 64 <565000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + }; > + > + opp-430000000 { > + opp-hz = /bits/ 64 <430000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + }; > + > + opp-355000000 { > + opp-hz = /bits/ 64 <355000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + }; > + > + opp-267000000 { > + opp-hz = /bits/ 64 <267000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + }; > + > + opp-180000000 { > + opp-hz = /bits/ 64 <180000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; > + }; > + }; > + }; > + > + adreno_smmu: iommu@5040000 { > + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; As per prior discussion "qcom,sc7180-smmu-v2" needs to be added to the bindings. > + reg = <0 0x05040000 0 0x10000>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>; > + > + clock-names = "bus", "iface", "mem_iface_clk"; As per discussion in v3 [1], "mem_iface_clk" is new and needs to be added to the bindings. Presumably that patch should be posted / Acked by Rob before we land this dts. Other than relying on un-posted bindings, this looks sane to me and this patch lets me bring the GPU up on my sc7180-based board. Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> -Doug [1] https://lore.kernel.org/r/1e29097cc1cdf18671379f6420f872b0@codeaurora.org _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-02-05 19:19 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-05 7:01 [PATCH v4 0/3] sc7180: Add A618 GPU bindings Sharat Masetty 2020-02-05 7:01 ` Sharat Masetty 2020-02-05 7:01 ` [PATCH v4 1/3] dt-bindings: clk: qcom: Add support for GPU GX GDSCR Sharat Masetty 2020-02-05 7:01 ` Sharat Masetty 2020-02-05 19:21 ` Doug Anderson 2020-02-05 19:21 ` Doug Anderson 2020-02-05 7:01 ` [PATCH v4 2/3] clk: qcom: gpucc: Add support for GX GDSC for SC7180 Sharat Masetty 2020-02-05 7:01 ` Sharat Masetty 2020-02-05 19:20 ` Doug Anderson 2020-02-05 19:20 ` Doug Anderson 2020-02-05 7:01 ` [PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob Sharat Masetty 2020-02-05 7:01 ` Sharat Masetty 2020-02-05 19:19 ` Doug Anderson [this message] 2020-02-05 19:19 ` Doug Anderson 2020-02-05 19:24 ` Doug Anderson 2020-02-05 19:24 ` Doug Anderson 2020-02-09 0:18 ` Bjorn Andersson 2020-02-09 0:18 ` Bjorn Andersson
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to='CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com' \ --to=dianders@chromium.org \ --cc=bjorn.andersson@linaro.org \ --cc=devicetree@vger.kernel.org \ --cc=dri-devel@freedesktop.org \ --cc=freedreno@lists.freedesktop.org \ --cc=jcrouse@codeaurora.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mka@chromium.org \ --cc=smasetty@codeaurora.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.