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From: "Xu, Anhua" <anhua.xu@intel.com>
To: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: [PATCH] drm/i915: fix reassignment of variable "intel_dp->DP"
Date: Tue, 21 Aug 2012 03:06:02 +0000	[thread overview]
Message-ID: <D908B1B9E708C047A32444772B58AE882218B1@SHSMSX101.ccr.corp.intel.com> (raw)

>From 952c95621b5fd95a629c36017c36ac9e6c40e839 Mon Sep 17 00:00:00 2001
From: Anhua Xu <anhua.xu@intel.com>
Date: Tue, 21 Aug 2012 11:00:57 +0800
Subject: [PATCH] drm/i915: fix reassignment of variable "intel_dp->DP"

This little regression was introduced by:
commit 417e822deee1d2bcd8a8a60660c40a0903713f2b
Author: Keith Packard <keithp@keithp.com>
Date:   Tue Nov 1 19:54:11 2011 -0700

    drm/i915: Treat PCH eDP like DP in most places

	PCH eDP has many of the same needs as regular PCH DP connections,
	including the DP_CTl bit settings, the TRANS_DP_CTL register.

The reachable tag for this commit is: v3.1-5461-g417e822

Signed-off-by: Anhua Xu <anhua.xu@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a6c426a..c060231 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -882,7 +882,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 	 * supposed to be read-only.
 	 */
 	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
-	intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 
 	/* Handle DP bits in common between all three register formats */
 
-- 
1.7.1

             reply	other threads:[~2012-08-21  3:06 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-21  3:06 Xu, Anhua [this message]
2012-08-21  7:06 ` [PATCH] drm/i915: fix reassignment of variable "intel_dp->DP" Daniel Vetter

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