From: Russell King <rmk+kernel@armlinux.org.uk> To: linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier <marc.zyngier@arm.com>, Florian Fainelli <f.fainelli@gmail.com>, Christoffer Dall <christoffer.dall@arm.com>, kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 12/15] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Date: Fri, 25 May 2018 15:01:24 +0100 [thread overview] Message-ID: <E1fMDHY-00073s-7i@rmk-PC.armlinux.org.uk> (raw) In-Reply-To: <20180525135938.GE17671@n2100.armlinux.org.uk> From: Marc Zyngier <marc.zyngier@arm.com> In order to avoid aliasing attacks against the branch predictor on Cortex-A15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> --- arch/arm/include/asm/kvm_mmu.h | 5 +++++ arch/arm/kvm/hyp/hyp-entry.S | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index d08ce9c41df4..48edb1f4ced4 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -306,6 +306,11 @@ static inline void *kvm_get_hyp_vector(void) return kvm_ksym_ref(__kvm_hyp_vector_bp_inv); } + case ARM_CPU_PART_CORTEX_A15: + { + extern char __kvm_hyp_vector_ic_inv[]; + return kvm_ksym_ref(__kvm_hyp_vector_ic_inv); + } #endif default: { diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S index e789f52a5129..918a05dd2d63 100644 --- a/arch/arm/kvm/hyp/hyp-entry.S +++ b/arch/arm/kvm/hyp/hyp-entry.S @@ -73,6 +73,28 @@ #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR .align 5 +__kvm_hyp_vector_ic_inv: + .global __kvm_hyp_vector_ic_inv + + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + W(add) sp, sp, #1 /* Reset 7 */ + W(add) sp, sp, #1 /* Undef 6 */ + W(add) sp, sp, #1 /* Syscall 5 */ + W(add) sp, sp, #1 /* Prefetch abort 4 */ + W(add) sp, sp, #1 /* Data abort 3 */ + W(add) sp, sp, #1 /* HVC 2 */ + W(add) sp, sp, #1 /* IRQ 1 */ + W(nop) /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + + b decode_vectors + + .align 5 __kvm_hyp_vector_bp_inv: .global __kvm_hyp_vector_bp_inv @@ -92,6 +114,8 @@ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ isb +decode_vectors: + #ifdef CONFIG_THUMB2_KERNEL /* * Yet another silly hack: Use VPIDR as a temp register. -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: rmk+kernel@armlinux.org.uk (Russell King) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 12/15] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Date: Fri, 25 May 2018 15:01:24 +0100 [thread overview] Message-ID: <E1fMDHY-00073s-7i@rmk-PC.armlinux.org.uk> (raw) In-Reply-To: <20180525135938.GE17671@n2100.armlinux.org.uk> From: Marc Zyngier <marc.zyngier@arm.com> In order to avoid aliasing attacks against the branch predictor on Cortex-A15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> --- arch/arm/include/asm/kvm_mmu.h | 5 +++++ arch/arm/kvm/hyp/hyp-entry.S | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index d08ce9c41df4..48edb1f4ced4 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -306,6 +306,11 @@ static inline void *kvm_get_hyp_vector(void) return kvm_ksym_ref(__kvm_hyp_vector_bp_inv); } + case ARM_CPU_PART_CORTEX_A15: + { + extern char __kvm_hyp_vector_ic_inv[]; + return kvm_ksym_ref(__kvm_hyp_vector_ic_inv); + } #endif default: { diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S index e789f52a5129..918a05dd2d63 100644 --- a/arch/arm/kvm/hyp/hyp-entry.S +++ b/arch/arm/kvm/hyp/hyp-entry.S @@ -73,6 +73,28 @@ #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR .align 5 +__kvm_hyp_vector_ic_inv: + .global __kvm_hyp_vector_ic_inv + + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + W(add) sp, sp, #1 /* Reset 7 */ + W(add) sp, sp, #1 /* Undef 6 */ + W(add) sp, sp, #1 /* Syscall 5 */ + W(add) sp, sp, #1 /* Prefetch abort 4 */ + W(add) sp, sp, #1 /* Data abort 3 */ + W(add) sp, sp, #1 /* HVC 2 */ + W(add) sp, sp, #1 /* IRQ 1 */ + W(nop) /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + + b decode_vectors + + .align 5 __kvm_hyp_vector_bp_inv: .global __kvm_hyp_vector_bp_inv @@ -92,6 +114,8 @@ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ isb +decode_vectors: + #ifdef CONFIG_THUMB2_KERNEL /* * Yet another silly hack: Use VPIDR as a temp register. -- 2.7.4
next prev parent reply other threads:[~2018-05-25 14:01 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-25 13:59 [PATCH v3 00/15] ARM Spectre variant 2 fixes Russell King - ARM Linux 2018-05-25 13:59 ` Russell King - ARM Linux 2018-05-25 14:00 ` [PATCH v3 01/15] ARM: add more CPU part numbers for Cortex and Brahma B15 CPUs Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:00 ` [PATCH v3 02/15] ARM: bugs: prepare processor bug infrastructure Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:00 ` [PATCH v3 03/15] ARM: bugs: hook processor bug checking into SMP and suspend paths Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:00 ` [PATCH v3 04/15] ARM: bugs: add support for per-processor bug checking Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:00 ` [PATCH v3 05/15] ARM: spectre: add Kconfig symbol for CPUs vulnerable to Spectre Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:00 ` [PATCH v3 06/15] ARM: spectre-v2: harden branch predictor on context switches Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:00 ` [PATCH v3 07/15] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit Russell King 2018-05-25 14:00 ` Russell King 2018-05-25 14:01 ` [PATCH v3 08/15] ARM: spectre-v2: harden user aborts in kernel space Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 15:47 ` Tony Lindgren 2018-05-25 15:47 ` Tony Lindgren 2018-05-25 15:52 ` Russell King - ARM Linux 2018-05-25 15:52 ` Russell King - ARM Linux 2018-05-25 16:01 ` Tony Lindgren 2018-05-25 16:01 ` Tony Lindgren 2018-05-25 16:15 ` Tony Lindgren 2018-05-25 16:15 ` Tony Lindgren 2018-05-25 14:01 ` [PATCH v3 09/15] ARM: spectre-v2: add firmware based hardening Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 14:01 ` [PATCH v3 10/15] ARM: spectre-v2: warn about incorrect context switching functions Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 14:01 ` [PATCH v3 11/15] ARM: KVM: invalidate BTB on guest exit for Cortex-A12/A17 Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 14:01 ` Russell King [this message] 2018-05-25 14:01 ` [PATCH v3 12/15] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Russell King 2018-05-25 14:01 ` [PATCH v3 13/15] ARM: spectre-v2: KVM: invalidate icache on guest exit for Brahma B15 Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 14:01 ` [PATCH v3 14/15] ARM: KVM: Add SMCCC_ARCH_WORKAROUND_1 fast handling Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 14:01 ` [PATCH v3 15/15] ARM: KVM: report support for SMCCC_ARCH_WORKAROUND_1 Russell King 2018-05-25 14:01 ` Russell King 2018-05-25 16:25 ` [PATCH v3 00/15] ARM Spectre variant 2 fixes Tony Lindgren 2018-05-25 16:25 ` Tony Lindgren
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