From: Inochi Amaoto <inochiama@outlook.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Chao Wei <chao.wei@sophgo.com>, Chen Wang <unicorn_wang@outlook.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Inochi Amaoto <inochiama@outlook.com> Cc: Jisheng Zhang <jszhang@kernel.org>, Liu Gui <kenneth.liu@sophgo.com>, Jingbao Qiu <qiujingbao.dlmu@gmail.com>, dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v9 6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC Date: Sat, 9 Mar 2024 17:02:56 +0800 [thread overview] Message-ID: <IA1PR20MB4953198222C3ABC2A2B6DE21BB262@IA1PR20MB4953.namprd20.prod.outlook.com> (raw) In-Reply-To: <IA1PR20MB4953512A4DCAF293D7B1CBC2BB262@IA1PR20MB4953.namprd20.prod.outlook.com> Add missing clocks of uart node for CV1800B and CV1812H. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 6ea1b2784db9..7c88cbe8e91d 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,cv1800.h> / { #address-cells = <1>; @@ -135,7 +136,8 @@ uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -145,7 +147,8 @@ uart1: serial@4150000 { compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -155,7 +158,8 @@ uart2: serial@4160000 { compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -165,7 +169,8 @@ uart3: serial@4170000 { compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -175,7 +180,8 @@ uart4: serial@41c0000 { compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; -- 2.44.0
WARNING: multiple messages have this Message-ID (diff)
From: Inochi Amaoto <inochiama@outlook.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Chao Wei <chao.wei@sophgo.com>, Chen Wang <unicorn_wang@outlook.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Inochi Amaoto <inochiama@outlook.com> Cc: Jisheng Zhang <jszhang@kernel.org>, Liu Gui <kenneth.liu@sophgo.com>, Jingbao Qiu <qiujingbao.dlmu@gmail.com>, dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v9 6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC Date: Sat, 9 Mar 2024 17:02:56 +0800 [thread overview] Message-ID: <IA1PR20MB4953198222C3ABC2A2B6DE21BB262@IA1PR20MB4953.namprd20.prod.outlook.com> (raw) In-Reply-To: <IA1PR20MB4953512A4DCAF293D7B1CBC2BB262@IA1PR20MB4953.namprd20.prod.outlook.com> Add missing clocks of uart node for CV1800B and CV1812H. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 6ea1b2784db9..7c88cbe8e91d 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,cv1800.h> / { #address-cells = <1>; @@ -135,7 +136,8 @@ uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -145,7 +147,8 @@ uart1: serial@4150000 { compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -155,7 +158,8 @@ uart2: serial@4160000 { compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -165,7 +169,8 @@ uart3: serial@4170000 { compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -175,7 +180,8 @@ uart4: serial@41c0000 { compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; -- 2.44.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-09 9:03 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-09 9:01 [PATCH v9 0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs Inochi Amaoto 2024-03-09 9:01 ` Inochi Amaoto 2024-03-09 9:02 ` [PATCH v9 1/6] dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC Inochi Amaoto 2024-03-09 9:02 ` Inochi Amaoto 2024-04-11 7:07 ` Stephen Boyd 2024-04-11 7:07 ` Stephen Boyd 2024-03-09 9:02 ` [PATCH v9 2/6] clk: sophgo: Add clock support for CV1800 SoC Inochi Amaoto 2024-03-09 9:02 ` Inochi Amaoto 2024-04-11 7:07 ` Stephen Boyd 2024-04-11 7:07 ` Stephen Boyd 2024-03-09 9:02 ` [PATCH v9 3/6] clk: sophgo: Add clock support for CV1810 SoC Inochi Amaoto 2024-03-09 9:02 ` Inochi Amaoto 2024-04-11 7:07 ` Stephen Boyd 2024-04-11 7:07 ` Stephen Boyd 2024-03-09 9:02 ` [PATCH v9 4/6] clk: sophgo: Add clock support for SG2000 SoC Inochi Amaoto 2024-03-09 9:02 ` Inochi Amaoto 2024-04-11 7:07 ` Stephen Boyd 2024-04-11 7:07 ` Stephen Boyd 2024-03-09 9:02 ` [PATCH v9 5/6] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC Inochi Amaoto 2024-03-09 9:02 ` Inochi Amaoto 2024-03-09 9:02 ` Inochi Amaoto [this message] 2024-03-09 9:02 ` [PATCH v9 6/6] riscv: dts: sophgo: add uart clock " Inochi Amaoto 2024-03-15 6:19 ` [PATCH v9 0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs Inochi Amaoto 2024-03-15 6:19 ` Inochi Amaoto 2024-04-11 7:38 ` (subset) " Inochi Amaoto 2024-04-11 7:38 ` Inochi Amaoto 2024-04-14 5:56 ` Michael Opdenacker 2024-04-14 5:56 ` Michael Opdenacker 2024-04-14 6:41 ` Inochi Amaoto 2024-04-14 6:41 ` Inochi Amaoto 2024-04-14 6:43 ` Inochi Amaoto 2024-04-14 6:43 ` Inochi Amaoto 2024-04-14 9:11 ` Michael Opdenacker 2024-04-14 9:11 ` Michael Opdenacker 2024-04-14 9:41 ` Inochi Amaoto 2024-04-14 9:41 ` Inochi Amaoto 2024-04-15 7:44 ` Michael Opdenacker 2024-04-15 7:44 ` Michael Opdenacker
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