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From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Openrisc <openrisc@lists.librecores.org>,
	"Tim \\'mithro\\' Ansell" <mithro@mithis.com>,
	Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PATCH v2 5/9] migration: Add VMSTATE_UINTTL_2DARRAY()
Date: Mon, 24 Apr 2017 07:40:53 +0900	[thread overview]
Message-ID: <a7a36b48f9e4c9f971556a7b71c056d2b25a41f0.1492986468.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1492986468.git.shorne@gmail.com>
In-Reply-To: <cover.1492986468.git.shorne@gmail.com>

In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 include/migration/cpu.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/migration/cpu.h b/include/migration/cpu.h
index f3d5dfc..a40bd35 100644
--- a/include/migration/cpu.h
+++ b/include/migration/cpu.h
@@ -18,6 +18,8 @@
     VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v)                \
+    VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v)
 #define VMSTATE_UINTTL_TEST(_f, _s, _t)                               \
     VMSTATE_UINT64_TEST(_f, _s, _t)
 #define vmstate_info_uinttl vmstate_info_uint64
@@ -37,6 +39,8 @@
     VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v)                \
+    VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v)
 #define VMSTATE_UINTTL_TEST(_f, _s, _t)                               \
     VMSTATE_UINT32_TEST(_f, _s, _t)
 #define vmstate_info_uinttl vmstate_info_uint32
@@ -48,5 +52,8 @@
     VMSTATE_UINTTL_EQUAL_V(_f, _s, 0)
 #define VMSTATE_UINTTL_ARRAY(_f, _s, _n)                              \
     VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2)                      \
+    VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0)
+
 
 #endif
-- 
2.9.3

WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v2 5/9] migration: Add VMSTATE_UINTTL_2DARRAY()
Date: Mon, 24 Apr 2017 07:40:53 +0900	[thread overview]
Message-ID: <a7a36b48f9e4c9f971556a7b71c056d2b25a41f0.1492986468.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1492986468.git.shorne@gmail.com>

In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 include/migration/cpu.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/migration/cpu.h b/include/migration/cpu.h
index f3d5dfc..a40bd35 100644
--- a/include/migration/cpu.h
+++ b/include/migration/cpu.h
@@ -18,6 +18,8 @@
     VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v)                \
+    VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v)
 #define VMSTATE_UINTTL_TEST(_f, _s, _t)                               \
     VMSTATE_UINT64_TEST(_f, _s, _t)
 #define vmstate_info_uinttl vmstate_info_uint64
@@ -37,6 +39,8 @@
     VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v)                \
+    VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v)
 #define VMSTATE_UINTTL_TEST(_f, _s, _t)                               \
     VMSTATE_UINT32_TEST(_f, _s, _t)
 #define vmstate_info_uinttl vmstate_info_uint32
@@ -48,5 +52,8 @@
     VMSTATE_UINTTL_EQUAL_V(_f, _s, 0)
 #define VMSTATE_UINTTL_ARRAY(_f, _s, _n)                              \
     VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2)                      \
+    VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0)
+
 
 #endif
-- 
2.9.3


  parent reply	other threads:[~2017-04-23 22:41 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-23 22:40 [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes Stafford Horne
2017-04-23 22:40 ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 1/9] target/openrisc: Implement EVBAR register Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 2/9] target/openrisc: Implement EPH bit Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 3/9] target/openrisc: Fixes for memory debugging Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 4/9] target/openrisc: add numcores and coreid support Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` Stafford Horne [this message]
2017-04-23 22:40   ` [OpenRISC] [PATCH v2 5/9] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 6/9] target/openrisc: implement shadow registers Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 7/9] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 8/9] target/openrisc: Implement full vmstate serialization Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-23 22:40 ` [Qemu-devel] [PATCH v2 9/9] target/openrisc: Remove duplicate features property Stafford Horne
2017-04-23 22:40   ` [OpenRISC] " Stafford Horne
2017-04-24  0:09 ` [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes no-reply
2017-04-24  0:09   ` [OpenRISC] " no-reply

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