From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: [Xen-devel] [PATCH 2/2] x86/mce: fix logic and comments around MSR_PPIN_CTL
Date: Mon, 2 Mar 2020 15:07:12 +0100 [thread overview]
Message-ID: <adaffda1-006b-4e84-62e0-a679adece844@suse.com> (raw)
In-Reply-To: <9687cc05-d3f5-c139-bbc4-a3eb05afdbea@suse.com>
From: Tony Luck <tony.luck@intel.com>
There are two implemented bits in the PPIN_CTL MSR:
Bit0: LockOut (R/WO)
Set 1 to prevent further writes to MSR_PPIN_CTL.
Bit 1: Enable_PPIN (R/W)
If 1, enables MSR_PPIN to be accessible using RDMSR.
If 0, an attempt to read MSR_PPIN will cause #GP.
So there are four defined values:
0: PPIN is disabled, PPIN_CTL may be updated
1: PPIN is disabled. PPIN_CTL is locked against updates
2: PPIN is enabled. PPIN_CTL may be updated
3: PPIN is enabled. PPIN_CTL is locked against updates
Code would only enable the X86_FEATURE_INTEL_PPIN feature for case "2".
When it should have done so for both case "2" and case "3".
Fix the final test to just check for the enable bit.
Also fix some of the other comments in this function.
Signed-off-by: Tony Luck <tony.luck@intel.com>
[Linux commit ???]
One of the adjusted comments doesn't exist in our code, and I disagree
with the adjustment to the other one and its associate code change: I
don't think there's a point trying to enable PPIN if the locked bit is
set. Hence it's just the main code change that gets pulled in, plus it
gets cloned to the AMD side.
Requested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
Note: If available by the time of committing I mean to insert the Linux
commit hash.
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -885,7 +885,7 @@ static void intel_init_ppin(const struct
rdmsr_safe(MSR_PPIN_CTL, val);
}
- if ( (val & (PPIN_ENABLE | PPIN_LOCKOUT)) != PPIN_ENABLE )
+ if ( !(val & PPIN_ENABLE) )
ppin_msr = 0;
else if ( c == &boot_cpu_data )
ppin_msr = MSR_PPIN;
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -329,7 +329,7 @@ amd_mcheck_init(struct cpuinfo_x86 *ci)
rdmsrl(MSR_AMD_PPIN_CTL, val);
}
- if ( (val & (PPIN_ENABLE | PPIN_LOCKOUT)) != PPIN_ENABLE )
+ if ( !(val & PPIN_ENABLE) )
ppin_msr = 0;
else if ( ci == &boot_cpu_data )
ppin_msr = MSR_AMD_PPIN;
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next prev parent reply other threads:[~2020-03-02 14:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 14:02 [Xen-devel] [PATCH 0/2] x86/mce: PPIN adjustments coming from Linux Jan Beulich
2020-03-02 14:06 ` [Xen-devel] [PATCH 1/2] x86/mce: add Xeon Icelake to list of CPUs that support PPIN Jan Beulich
2020-03-02 14:09 ` Andrew Cooper
2020-03-02 14:07 ` Jan Beulich [this message]
2020-03-02 14:26 ` [Xen-devel] [PATCH 2/2] x86/mce: fix logic and comments around MSR_PPIN_CTL Andrew Cooper
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