From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Andy Gross <agross@kernel.org> Cc: Stephen Boyd <swboyd@chromium.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Subject: [PATCH 1/2] arm64: dts: qcom: sc7180: Support ETMv4 power management Date: Fri, 15 May 2020 16:21:36 +0530 [thread overview] Message-ID: <b0a2ac4ffefe7d3e216a83ab56867620f120ff08.1589539293.git.saiprakash.ranjan@codeaurora.org> (raw) In-Reply-To: <cover.1589539293.git.saiprakash.ranjan@codeaurora.org> Now that deep idle states are properly supported on SC7180, we need to add "coresight-loses-context-with-cpu" property to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- Resending this because the last patch sent here - https://lore.kernel.org/patchwork/patch/1230367/ seems to have added "coresight-loses-context-with-cpu" to replicator node instead of etm7 node. --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4069bb1c93af..8b3707347547 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1656,6 +1656,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1674,6 +1675,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1692,6 +1694,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1710,6 +1713,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1728,6 +1732,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1746,6 +1751,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1764,6 +1770,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1782,6 +1789,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Andy Gross <agross@kernel.org> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Stephen Boyd <swboyd@chromium.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] arm64: dts: qcom: sc7180: Support ETMv4 power management Date: Fri, 15 May 2020 16:21:36 +0530 [thread overview] Message-ID: <b0a2ac4ffefe7d3e216a83ab56867620f120ff08.1589539293.git.saiprakash.ranjan@codeaurora.org> (raw) In-Reply-To: <cover.1589539293.git.saiprakash.ranjan@codeaurora.org> Now that deep idle states are properly supported on SC7180, we need to add "coresight-loses-context-with-cpu" property to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- Resending this because the last patch sent here - https://lore.kernel.org/patchwork/patch/1230367/ seems to have added "coresight-loses-context-with-cpu" to replicator node instead of etm7 node. --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4069bb1c93af..8b3707347547 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1656,6 +1656,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1674,6 +1675,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1692,6 +1694,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1710,6 +1713,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1728,6 +1732,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1746,6 +1751,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1764,6 +1770,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -1782,6 +1789,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-15 10:52 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-15 10:51 [PATCH 0/2] arm64: dts: qcom: sc7180: Add support for ETMv4 PM and skipping power up Sai Prakash Ranjan 2020-05-15 10:51 ` Sai Prakash Ranjan 2020-05-15 10:51 ` Sai Prakash Ranjan [this message] 2020-05-15 10:51 ` [PATCH 1/2] arm64: dts: qcom: sc7180: Support ETMv4 power management Sai Prakash Ranjan 2020-05-15 10:55 ` Sai Prakash Ranjan 2020-05-15 10:55 ` Sai Prakash Ranjan 2020-05-18 18:51 ` Bjorn Andersson 2020-05-18 18:51 ` Bjorn Andersson 2020-05-18 19:08 ` Sai Prakash Ranjan 2020-05-18 19:08 ` Sai Prakash Ranjan 2020-05-18 22:35 ` Bjorn Andersson 2020-05-18 22:35 ` Bjorn Andersson 2020-05-15 10:51 ` [PATCH 2/2] arm64: dts: qcom: sc7180: Add support to skip powering up of ETM Sai Prakash Ranjan 2020-05-15 10:51 ` Sai Prakash Ranjan 2020-06-09 13:54 ` Sai Prakash Ranjan 2020-06-09 13:54 ` Sai Prakash Ranjan
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=b0a2ac4ffefe7d3e216a83ab56867620f120ff08.1589539293.git.saiprakash.ranjan@codeaurora.org \ --to=saiprakash.ranjan@codeaurora.org \ --cc=agross@kernel.org \ --cc=bjorn.andersson@linaro.org \ --cc=coresight@lists.linaro.org \ --cc=devicetree@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mathieu.poirier@linaro.org \ --cc=mike.leach@linaro.org \ --cc=robh+dt@kernel.org \ --cc=suzuki.poulose@arm.com \ --cc=swboyd@chromium.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.