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From: Michal Simek <michal.simek@amd.com>
To: <u-boot@lists.denx.de>, <git@xilinx.com>
Cc: Christian Kohn <christian.kohn@xilinx.com>,
	Soren Brinkmann <soren.brinkmann@xilinx.com>
Subject: [PATCH] ARM: zynq: DT: Enable all FCLKs by default
Date: Wed, 12 Oct 2022 11:30:33 +0200	[thread overview]
Message-ID: <b1308dc1f14f8eb24662019f7376c959e5e763b8.1665567031.git.michal.simek@amd.com> (raw)

From: Christian Kohn <christian.kohn@xilinx.com>

The fclk-enable property is set to 0 which disables all FCLKs.
Enable all FCLKs so they can be used as clock sources in the
programmable logic.

Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/arm/dts/zynq-7000.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index edc147d63f1e..f72ef526f057 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -340,7 +340,7 @@
 				u-boot,dm-pre-reloc;
 				#clock-cells = <1>;
 				compatible = "xlnx,ps7-clkc";
-				fclk-enable = <0>;
+				fclk-enable = <0xf>;
 				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
-- 
2.36.1


             reply	other threads:[~2022-10-12  9:30 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-12  9:30 Michal Simek [this message]
2022-10-25  8:29 ` [PATCH] ARM: zynq: DT: Enable all FCLKs by default Michal Simek
  -- strict thread matches above, loose matches on Subject: below --
2022-07-07 10:50 Michal Simek
2022-07-07 12:31 ` Tom Rini
2022-07-07 12:39   ` Michal Simek

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