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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v1 10/16] target/riscv: Specify the XLEN for CPUs
Date: Fri, 23 Oct 2020 08:33:40 -0700	[thread overview]
Message-ID: <b586d3c656319962c5cd4d73bd17e6d03bdd1301.1603467169.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1603467169.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32234d4a70..8f8c568974 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -157,22 +157,36 @@ static void riscv_base_cpu_init(Object *obj)
     set_misa(env, 0);
 }
 
-static void rvxx_sifive_u_cpu_init(Object *obj)
+#ifdef TARGET_RISCV64
+static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
-static void rvxx_sifive_e_cpu_init(Object *obj)
+static void rv64_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
+#else
+static void rv32_sifive_u_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+}
 
-#if defined(TARGET_RISCV32)
+static void rv32_sifive_e_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
 
 static void rv32_ibex_cpu_init(Object *obj)
 {
@@ -190,7 +204,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
-
 #endif
 
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -647,13 +660,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
 #if defined(TARGET_RISCV32)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 #elif defined(TARGET_RISCV64)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_sifive_e_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 #endif
 };
 
-- 
2.28.0



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com
Subject: [PATCH v1 10/16] target/riscv: Specify the XLEN for CPUs
Date: Fri, 23 Oct 2020 08:33:40 -0700	[thread overview]
Message-ID: <b586d3c656319962c5cd4d73bd17e6d03bdd1301.1603467169.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1603467169.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32234d4a70..8f8c568974 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -157,22 +157,36 @@ static void riscv_base_cpu_init(Object *obj)
     set_misa(env, 0);
 }
 
-static void rvxx_sifive_u_cpu_init(Object *obj)
+#ifdef TARGET_RISCV64
+static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
-static void rvxx_sifive_e_cpu_init(Object *obj)
+static void rv64_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
+#else
+static void rv32_sifive_u_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+}
 
-#if defined(TARGET_RISCV32)
+static void rv32_sifive_e_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
 
 static void rv32_ibex_cpu_init(Object *obj)
 {
@@ -190,7 +204,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
-
 #endif
 
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -647,13 +660,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
 #if defined(TARGET_RISCV32)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 #elif defined(TARGET_RISCV64)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_sifive_e_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 #endif
 };
 
-- 
2.28.0



  parent reply	other threads:[~2020-10-23 16:05 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-23 15:33 [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess Alistair Francis
2020-10-23 15:33 ` Alistair Francis
2020-10-23 15:33 ` [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:55   ` Bin Meng
2020-10-26  8:55     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 02/16] riscv: spike: Remove target macro conditionals Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:55   ` Bin Meng
2020-10-26  8:55     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 03/16] riscv: virt: " Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:55   ` Bin Meng
2020-10-26  8:55     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 04/16] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:55   ` Bin Meng
2020-10-26  8:55     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 05/16] hw/riscv: virt: " Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:55   ` Bin Meng
2020-10-26  8:55     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 06/16] hw/riscv: spike: " Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:55   ` Bin Meng
2020-10-26  8:55     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 07/16] hw/riscv: sifive_u: " Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-26 15:12     ` Alistair Francis
2020-10-26 15:12       ` Alistair Francis
2020-10-23 15:33 ` [PATCH v1 08/16] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-26 15:16     ` Alistair Francis
2020-10-26 15:16       ` Alistair Francis
2020-10-23 15:33 ` [PATCH v1 09/16] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-23 15:33 ` Alistair Francis [this message]
2020-10-23 15:33   ` [PATCH v1 10/16] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 11/16] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 12/16] target/riscv: cpu_helper: " Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-27 20:25     ` Alistair Francis
2020-10-27 20:25       ` Alistair Francis
2020-10-23 15:33 ` [PATCH v1 13/16] target/riscv: csr: " Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 14/16] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-23 15:33 ` [PATCH v1 15/16] target/riscv: Convert the get/set_field() to support 64-bit values Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-23 15:33 ` [PATCH v1 16/16] target/riscv: Consolidate *statush registers Alistair Francis
2020-10-23 15:33   ` Alistair Francis
2020-10-23 16:55   ` Richard Henderson
2020-10-23 16:55     ` Richard Henderson
2020-10-26  8:56   ` Bin Meng
2020-10-26  8:56     ` Bin Meng
2020-10-26  8:55 ` [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess Bin Meng
2020-10-26  8:55   ` Bin Meng
2020-10-26 16:32   ` Alistair Francis
2020-10-26 16:32     ` Alistair Francis

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