From: Quentin Schulz <quentin.schulz@free-electrons.com> To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@free-electrons.com, linux@armlinux.org.uk, boris.brezillon@free-electrons.com, perex@perex.cz, tiwai@suse.com Cc: cyrille.pitchen@wedev4u.fr, thomas.petazzoni@free-electrons.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-kernel@lists.infradead.org, Quentin Schulz <quentin.schulz@free-electrons.com> Subject: [PATCH v4 1/9] clk: at91: clk-generated: remove useless divisor loop Date: Tue, 25 Jul 2017 09:37:02 +0200 [thread overview] Message-ID: <b9d92004d22f745e8acde0599359d67538c006a9.1500968090.git-series.quentin.schulz@free-electrons.com> (raw) In-Reply-To: <cover.c8ce78c15296190b2aa5c452c0c4512528e28518.1500968090.git-series.quentin.schulz@free-electrons.com> In-Reply-To: <cover.c8ce78c15296190b2aa5c452c0c4512528e28518.1500968090.git-series.quentin.schulz@free-electrons.com> The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation). We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- drivers/clk/at91/clk-generated.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index f0b7ae9..ef4b4e0 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -124,19 +124,18 @@ static int clk_generated_determine_rate(struct clk_hw *hw, (gck->range.max && min_rate > gck->range.max)) continue; - for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { - tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); - tmp_diff = abs(req->rate - tmp_rate); - - if (best_diff < 0 || best_diff > tmp_diff) { - best_rate = tmp_rate; - best_diff = tmp_diff; - req->best_parent_rate = parent_rate; - req->best_parent_hw = parent; - } - - if (!best_diff || tmp_rate < req->rate) - break; + div = DIV_ROUND_CLOSEST(parent_rate, req->rate); + if (!div) + tmp_rate = parent_rate; + else + tmp_rate = parent_rate / div; + tmp_diff = abs(req->rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + best_rate = tmp_rate; + best_diff = tmp_diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; } if (!best_diff) -- git-series 0.9.1
WARNING: multiple messages have this Message-ID (diff)
From: quentin.schulz@free-electrons.com (Quentin Schulz) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/9] clk: at91: clk-generated: remove useless divisor loop Date: Tue, 25 Jul 2017 09:37:02 +0200 [thread overview] Message-ID: <b9d92004d22f745e8acde0599359d67538c006a9.1500968090.git-series.quentin.schulz@free-electrons.com> (raw) In-Reply-To: <cover.c8ce78c15296190b2aa5c452c0c4512528e28518.1500968090.git-series.quentin.schulz@free-electrons.com> The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation). We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- drivers/clk/at91/clk-generated.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index f0b7ae9..ef4b4e0 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -124,19 +124,18 @@ static int clk_generated_determine_rate(struct clk_hw *hw, (gck->range.max && min_rate > gck->range.max)) continue; - for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { - tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); - tmp_diff = abs(req->rate - tmp_rate); - - if (best_diff < 0 || best_diff > tmp_diff) { - best_rate = tmp_rate; - best_diff = tmp_diff; - req->best_parent_rate = parent_rate; - req->best_parent_hw = parent; - } - - if (!best_diff || tmp_rate < req->rate) - break; + div = DIV_ROUND_CLOSEST(parent_rate, req->rate); + if (!div) + tmp_rate = parent_rate; + else + tmp_rate = parent_rate / div; + tmp_diff = abs(req->rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + best_rate = tmp_rate; + best_diff = tmp_diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; } if (!best_diff) -- git-series 0.9.1
next prev parent reply other threads:[~2017-07-25 7:41 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-07-25 7:37 [PATCH v4 0/9] add support for Sama5d2 audio PLLs and enable ClassD Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz [this message] 2017-07-25 7:37 ` [PATCH v4 1/9] clk: at91: clk-generated: remove useless divisor loop Quentin Schulz 2017-07-25 15:28 ` Nicolas Ferre 2017-07-25 15:28 ` Nicolas Ferre 2017-07-25 15:28 ` Nicolas Ferre 2017-07-25 7:37 ` [PATCH v4 2/9] dt-bindings: clk: at91: add audio plls to the compatible list Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 15:45 ` Nicolas Ferre 2017-07-25 15:45 ` Nicolas Ferre 2017-07-25 15:45 ` Nicolas Ferre 2017-07-25 7:37 ` [PATCH v4 3/9] clk: at91: add audio pll clock drivers Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 7:37 ` [PATCH v4 4/9] ARM: dts: at91: sama5d2: add classd nodes Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-26 6:59 ` Alexandre Belloni 2017-07-26 6:59 ` Alexandre Belloni 2017-07-26 6:59 ` Alexandre Belloni 2017-07-25 7:37 ` [PATCH v4 5/9] clk: at91: clk-generated: create function to find best_diff Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 15:33 ` Nicolas Ferre 2017-07-25 15:33 ` Nicolas Ferre 2017-07-25 15:33 ` Nicolas Ferre 2017-07-25 7:37 ` [PATCH v4 6/9] clk: at91: clk-generated: make gclk determine audio_pll rate Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 15:37 ` Nicolas Ferre 2017-07-25 15:37 ` Nicolas Ferre 2017-07-25 15:37 ` Nicolas Ferre 2017-07-25 7:37 ` [PATCH v4 7/9] ASoC: atmel-classd: remove aclk clock from DT binding Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 15:38 ` Nicolas Ferre 2017-07-25 15:38 ` Nicolas Ferre 2017-07-25 15:38 ` Nicolas Ferre 2017-07-25 7:37 ` [PATCH v4 8/9] ASoC: atmel-classd: remove aclk clock Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-25 15:40 ` Nicolas Ferre 2017-07-25 15:40 ` Nicolas Ferre 2017-07-25 15:40 ` Nicolas Ferre 2017-07-25 7:37 ` [PATCH v4 9/9] ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd Quentin Schulz 2017-07-25 7:37 ` Quentin Schulz 2017-07-26 6:59 ` Alexandre Belloni 2017-07-26 6:59 ` Alexandre Belloni 2017-07-25 15:44 ` [PATCH v4 0/9] add support for Sama5d2 audio PLLs and enable ClassD Nicolas Ferre 2017-07-25 15:44 ` Nicolas Ferre 2017-07-25 15:44 ` Nicolas Ferre 2017-07-26 6:57 ` Alexandre Belloni 2017-07-26 6:57 ` Alexandre Belloni 2017-07-26 6:57 ` Alexandre Belloni 2017-07-26 7:08 ` Quentin Schulz 2017-07-26 7:08 ` Quentin Schulz
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