[PATCH] PCI: Change message to debug level in pci_set_cacheline_size

From: Heiner Kallweit <hkallweit1@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: [PATCH] PCI: Change message to debug level in pci_set_cacheline_size
Date: Tue, 8 Dec 2020 18:57:02 +0100	[thread overview]
Message-ID: <be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com> (raw)

Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an
annnoying message like the following that results in user questions
whether something is broken.
xhci_hcd 0000:00:15.0: cache line size of 64 is not supported

Root cause of the message is that on several (most?) chips the
cache line size register is hard-wired to 0.

Change this message to debug level, an interested caller can still
inform the user (if deemed helpful) based on the return code.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
 drivers/pci/pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b7f0883d6..9a5500287 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4324,7 +4324,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
 	if (cacheline_size == pci_cache_line_size)
 		return 0;
 
-	pci_info(dev, "cache line size of %d is not supported\n",
+	pci_dbg(dev, "cache line size of %d is not supported\n",
 		   pci_cache_line_size << 2);
 
 	return -EINVAL;
-- 
2.29.2

